SST26VF032B-104ISLASHSM datasheet(61/82 Pages) MICROCHIP

61 / 82 page

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DS20005218K-page 61

SST26VF032B/SST26VF032BA

31H

A15:A8

20H

4 Kbyte Erase Opcode

32H

A16

F1H

Supports (1-1-2) Fast Read

(1-1-2) Fast Read NOT supported

(1-1-2) Fast Read supported

A18:A17

Address Bytes

Number of bytes used in addressing Flash array read, write and erase

00: 3-byte only addressing

01: 3- or 4-byte addressing (e.g. defaults to 3-Byte mode; enters 4-Byte

mode on command)

10: 4-byte only addressing

11: Reserved

A19

Supports Double Transfer Rate (DTR) Clocking

Indicates the device supports some type of double transfer rate clocking.

DTR NOT supported

DTR Clocking supported

A20

Supports (1-2-2) Fast Read

Device supports single input opcode, dual input address, and dual output

data Fast Read.

(1-2-2) Fast Read NOT supported.

(1-2-2) Fast Read supported.

A21

Supports (1-4-4) Fast Read

Device supports single input opcode, quad input address, and quad out-

put data Fast Read

(1-4-4) Fast Read NOT supported.

(1-4-4) Fast Read supported.

A22

Supports (1-1-4) Fast Read

Device supports single input opcode & address and quad output data

Fast Read.

(1-1-4) Fast Read NOT supported.

(1-1-4) Fast Read supported.

A23

Unused. Contains ‘1’ can not be changed.

33H

A31:A24

FFH

Unused. Contains FF can not be changed

JEDEC Flash Parameter Table: 2nd DWORD

34H

A7:A0

FFH

Flash Memory Density

SST26VF032B/032BA = 01FFFFFFH

35H

A15:A8

FFH

36H

A23:A16

FFH

37H

A31:A24

01H

JEDEC Flash Parameter Table: 3rd DWORD

38H

A4:A0

44H

(1-4-4) Fast Read Number of Wait states (dummy clocks) needed

before valid output

00100b: 4 dummy clocks (16 dummy bits) are needed with a quad input

address phase instruction

A7:A5

Quad Input Address Quad Output (1-4-4) Fast Read Number of Mode

Bits

010b: 2 dummy clocks (8 mode bits) are needed with a single input

opcode, quad input address and quad output data Fast Read Instruction.

39H

A15:A8

EBH

(1-4-4) Fast Read Opcode

Opcode for single input opcode, quad input address, and quad output

data Fast Read.

TABLE 11-1:

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED)

Address

Bit Address

Data

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