September 2006

XRT8000

Clock Synchronizer/Adapter for

Communications

Rev.1.11

E

1999--2006

EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 z www.exar.com

FEATURES

D

Clock Adaptation for Most Popular

Telecommunication Frequencies

D

Wide Input Frequency Range

D

Programmable Output Frequencies

D

Less than 0.05UI Wide Band Output Jitter

D

Low Power Operation (5V and 3.3V)

D

Maximum Lock Time of 45mS

D

Cascadable

D

No External Components Needed

D

Lock Detect Indication Pin

APPLICATIONS

D

DSU’s, CSU’s and Access Equipment

D

ISDN Terminals

D

Concentrators and Multiplexers

GENERAL DESCRIPTION

The XRT8000 is a dual phase-locked loop chip that

generates two simultaneous, very low jitter, output clocks

for synchronization applications in wide area networking

systems. The outputs are phase locked to the input

signal. The chip has four basic modes of operation;

referred to as master (FORWARD, REVERSE) and slave

(FORWARD, REVERSE) modes (See Figure 1). In the

FORWARD mode it accepts up to 16th harmonic of either

1.544MHz or 2.048MHz as input reference and generates

1.2kHz and multiples of 2.4kHz, 56kHz or 64kHz. In the

REVERSE mode an input clock of 56kHz or 64kHz is used

to generate 1.544MHz or 2.048MHz output clocks. The

SLAVE (FORWARD, REVERSE) modes generate the

same output frequencies as the MASTER (FORWARD/

is 8kHz. An optional divide by eight can be enabled at

each of the outputs.

The input and output frequency selection can be done

through a serial microprocessor interface. The XRT8000

is available in either 18 pin SOIC package or 18 pin plastic

DIP.

ORDERING INFORMATION

Part No.

Package

Operating Temperature

Range

XRT8000IP

18 Lead 300 Mil PDIP

-40°C to +85°C

XRT8000ID

18 Lead 300 Mil JEDEC SOIC

-40°C to +85°C

n x 1.544{T1}

n x 2.048{E1}

1 <= n <= 16

K x 56kHz

K x 64kHz

1.2kHz

2.4 x K

to

43.2kHz

1 <= K <= 32

MASTER FORWARD

T1 (1.544)

E1 (2.048)

56kHz

64kHz

MASTER REVERSE

8kHz

B

A/ B

A

Figure 1. System Diagram

1 <= K <= 18

XRT8000

XRT8000

XRT8000

CLK2

CLK2

CLK2

CLK1

CLK1

CLK1

SYNC 8kHz

SLAVE

FORWARD/REVERSE

or

SYNC

SYNC