XRT8000

13

Rev. 1.11

Table 6 presents information on the delay between the rising edge of SYNC and the CLK1 or CLKL output signals. It is

important to note that this delay behaves as a function of the settings within the CR3 register.

T values (nS)

SEL14~SEL10

K

Kx56 MODE

Kx64 MODE

00000

1

372

326

00001

2

372

326

00010

3

372

326

00011

4

372

326

00100

5

446

391

00101

6

372

326

00110

7

319

279

00111

8

279

244

01000

9

496

434

01001

10

446

301

01010

11

406

355

01011

12

372

326

01100

13

343

301

01101

14

319

279

01110

15

298

260

01111

16

279

244

10000

17

525

460

10001

18

496

434

10010

19

470

411

10011

20

446

391

10100

21

425

372

10101

22

406

355

10110

23

388

340

10111

24

372

326

11000

25

357

312

11001

26

343

301

11010

27

331

289

11011

28

319

279

11100

29

308

279

11101

30

298

260

11110

31

288

252

11111

32

279

244

Notes:

with the divide by eight enabled.

operating in the REVERSE Mode.

Table 6. Delay Time Between SYNC and CLK1 or CLK2