XRT8000

3

Rev. 1.11

PIN CONFIGURATION

SCLK

CSB

SDI

GND

CLK2

LOCKDET

SDO

SYNC

GND

GND

CLK1

MSB

GND

18 Lead PDIP (0.300”)

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

18 Lead SOIC (Jedec, 0.300”)

SCLK

CSB

SDI

GND

CLK2

LOCKDET

SDO

SYNC

GND

GND

CLK1

MSB

GND

18

1

10

9

2

3

4

5

6

7

15

14

13

12

11

17

16

8

PIN DESCRIPTION

Symbol

Pin#

Type

Description

SDO

1

O

Serial Data Output (Microprocessor Serial Interface). Data output from the command reg-

isters.

SYNC

2

O

be used to synchronize other XRT8000 which are configured in slave modes.

3

I

Reference Frequency Input.

GND

4

Digital Ground.

GND

5

Digital Ground.

CLK1

6

O

Clock 1. Output of the phase-locked loop 1.

7

Digital Positive Power Supply.

MSB

8

I

Master/Slave Mode Select Input. If this input is high, then the MASTER mode is selected. If

this input is low, then the SLAVE mode is enabled. This pin is internally pulled up via 100KW

resistor.

GND

9

Analog Ground.

10

Analog Positive Supply.

LOCKDET

11

O

Lock Detect. This output is high when both phase-locked loops are in lock and will go low if

either one of the phase locked loops loses lock.

12

Digital Positive Power Supply.

CLK2

13

O

Clock 2. Output of the phase-locked loop 2.

GND

14

Digital Ground.

15

Digital Positive Power Supply.

SDI

16

I

Serial Data Input (Microprocessor Serial Interface) Data input to the command registers.

CSB

17

I

Chip Select Not (Microprocessor Serial Interface) . When this input is low the data in and

out will be shifted in the appropriate registers. Internal pull up (100K).

SCLK

18

I

Serial Clock Input (Microprocessor Serial Interface) . This clock will serve as a reference

to the data streams to SDI and SDO (the positive edge of SCLK is used to latch the data).