XRT83SL314 datasheet(69/83 Pages) EXAR

69 / 83 page

XRT83SL314

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

REV. 1.0.1

TABLE 45: MICROPROCESSOR REGISTER 0XE4H BIT DESCRIPTION

TABLE 46: MICROPROCESSOR REGISTER 0XE5H BIT DESCRIPTION

GLOBAL REGISTER (0XE4H)

BIT

NAME

FUNCTION

Type

Default

Value

(HW reset)

MclkT1out1

MclkT1out0

MCLKT1OUT Select

MclkT1out[1:0] is used to program the MCLKT1out pin. By default,

the output clock is 1.544MHz.

00 = 1.544MHz

01 = 3.088MHz

10 = 6.176MHz

11 = 12.352MHz

R/W

MclkE1out1

MclkE1out0

MCLKE1OUT Select

MclkE1out[1:0] is used to program the MCLKE1out pin.

default, the output clock is 2.048MHz.

00 = 2.048MHz

01 = 4.096MHz

10 = 8.192MHz

11 = 16.384MHz

R/W

Reserved

This Register Bit is Not Used

R/W

Reserved

This Register Bit is Not Used

R/W

Reserved

This Register Bit is Not Used

R/W

Reserved

This Register Bit is Not Used

R/W

GLOBAL REGISTER (0XE5H)

BIT

NAME

FUNCTION

Type

Default

Value

(HW reset)

LCV/OFLW Line Code Violation / Counter Overflow Monitor Select

This bit is used to select the monitoring activity between the LCV

and the counter overflow status. When the 16-bit LCV counter sat-

urates, the counter overflow condition is activated. By default, the

LCV activity is monitored by bit D4 in register 0x05h.

0 = Monitoring LCV

1 = Monitoring the counter overflow status

R/W

CNTRDEN Line Code Violation Counter Read Enable

This bit enables the 16-bit LCV counter contents to be read from

bits D[7:0] in register 0xE8h. If a counter reaches full scale, it sat-

urates and remains at FFFFh until a reset is initiated in register

0xE6h. By default, the LCV counter readback function is disabled.

0 = Disabled

1 = Enables the 16-bit LCV Counters for Readback

R/W

Reserved

This Register Bit is Not Used

R/W

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