34701 datasheet(17/38 Pages) FREESCALE

17 / 38 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

34701

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

POWER SUPPLY PIN (VDDI)

Internal supply voltage. A ceramic low ESR 1uF 6V X5R or

X7R capacitor is recommended.

ADDRESS PIN (ADDR)

The ADDR pin is used to set the address of the device

when used in an I2C communication. This pin can either be

tied to VDDI or grounded through a 10 k

Ω resistor. Refer to

I2C Bus Operation on page 26 for more information on this

pin.

ENABLE 1 AND 2 PINS (EN1 AND EN2)

These two pins permit positive logic control of the Enable

function and selection of the Power Sequencing mode

concurrently. Table 5 depicts the EN1 and EN2 function and

Power Sequencing mode selection.

Both EN1 and EN2 pins have internal pull-down resistors

and both can withstand a short circuit to the supply voltage,

6.0 V.

RESET TIMER PIN (RT)

The Reset Timer power-up delay (RT) pin is used to set

the delay between the time when the LDO and switcher

outputs are active and stable and the RST output is released.

An external resistor and capacitor are used to program the

timer. The power-up delay can be obtained by using the

following formula:

tD = 10 ms + RtCt

Where Rt is the Reset Timer programming resistor and Ct

is the Reset Timer programming capacitor, both connected in

parallel from RT to ground.

Note

Observe the maximum Ct value and expect reduced

accuracy if Rt is less than 10 kΩ.

RESET OUTPUT PIN (RST)

The Reset Control circuit monitors both the switching

regulator and the LDO feedback voltages. It is an open drain

output and has to be pulled up to some supply voltage (e.g.,

the output of the LDO) by an external resistor.

The Reset Control circuit supervises both output

voltages—the linear regulator output VLDO and the switching

regulator output VOUT. When either of these two regulators

is out of regulation (high or low), the RST pin is pulled low.

There is a 20 µs delay filter preventing erroneous resets.

During power-up sequencing, RST is held low until the Reset

Timer times out.

CLOCK SELECTION PIN (CLKSEL)

This pin sets the CLKSYN pin as either an oscillator output

or a synchronization input pin. The CLKSEL pin is also used

for the I2C address selection.

CLOCK SYNCHRONIZATION PIN (CLKSYN)

Oscillator output/synchronization input pin.

Table 5.

Operating Mode Selection

EN1

EN2

Operating Mode

Regulators Disabled

Standard Power Sequencing

Inverted Power Sequencing

No Power Sequencing,

Regulators Enabled

34701 датащи(PDF) 17 Page - Freescale Semiconductor, Inc

34701 датащи(HTML) 17 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

датащи скачать

ссылки URL