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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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34701 датащи(PDF) 23 Page - Freescale Semiconductor, Inc |
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34701 датащи(HTML) 23 Page - Freescale Semiconductor, Inc |
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23 / 38 page  Analog Integrated Circuit Device Data Freescale Semiconductor 23 34701 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Figure 18. Standard Power Up/Down Sequence in +5.0 V Supply System STANDARD POWER SEQUENCING When the power supply IC operates in the Standard Power Sequencing mode, the switcher output provides the core voltage for the microprocessor. This situation and operating conditions are illustrated in Figures 17 and 18. Table 5, page 17, shows the Power Sequencing mode selection. INVERTED POWER SEQUENCING When the power supply IC is operating in the Inverted Power Sequencing mode, the linear regulator (LDO) output provides the core voltage for the microprocessor, as illustrated in Figure 19. Table 5 shows the Power Sequencing mode selection. Figure 19. Inverted Power Up/Down Sequence in +5.0 V Supply System ASSUMED REQUIREMENTS 1. I/O supply voltage not to exceed core voltage by more than 2.0 V. 2. Core supply voltage not to exceed I/O voltage by more than 0.4 V. Methods of Control The 34701 has several methods of monitoring and controlling the regulator output voltages, as described in the paragraphs below. Power sequencing control is also achieved through the intrinsic operation of the regulators. The EN1 and EN2 pins can be used to select the proper power sequencing mode required by the powered system or to disable the power sequencing (refer to Table 5). Intrinsic Operation For both the LDO and switcher, whenever the output voltage is below the regulation point, the LDO external Pass MOSFET is on, or the Buck High-Side MOSFET is on at a duty cycle controlled by the switcher. Because these devices are MOSFETs, current can flow in either direction, balancing the voltages via the common supply pin. The ability to maintain the MOSFETs on is dependent on the available gate voltage, and thus the size of the boost regulator storage capacitor. ∆V = 2.1 V Max. Lead ∆V = 0.4 V Max. Lag ∆V = 0.4 V Max. Lag 1.8V Start-Up 3.3 V I/O Voltage (VLDO) 1.5 V Core Voltage (VOUT) 5.0 V Input Supply ∆V = 2.1 V Max. Lead RT VBD VDDH (I/Os) VDDL (Core) MCU 34701 5.0 V Input VIN2 CLKSEL FREQ GND SDA SCL ADDR VIN1 LDRV LDO LFB CS RST SW PGND INV VBST BOOT VOUT CLKSYN Optional EN1 EN2 VBST VDDI 3.3 V 1.5 V 5.0 V ∆V = 2.1 V Max. Lead ∆V = 0.4 V Max. Lag ∆V = 0.4 V Max. Lag 1.8V Start-Up 3.3 V I/O Voltage (VOUT) 1.5 V Core Voltage(VLDO) 5.0 V Input Supply ∆V = 2.1 V Max. Lead RT VBD VDDH (I/Os) VDDL (Core) MCU 34701 5.0 V Input VIN2 CLKSEL FREQ GND SDA SCL ADDR VIN1 LDRV LDO LFB CS RST SW PGND INV VBST BOOT VOUT CLKSYN Optional EN1 EN2 VBST VDDI 3.3 V 1.5 V 5.0 V |
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