Philips Semiconductors

Preliminary specification

MIPS

PR31100

Highly integrated embedded processor

1996 Aug 07

8

PIN DESCRIPTIONS

Overview

The PR31100 processor contains 208 pins consisting of input, output, bi–directional, and power and ground pins. These pins are used to

support various functions. The following sections will describe the function of each pin including any special power–down considerations for

each pin.

Pins

The PR31100 PROCESSOR contains 208 total pins, consisting of 136 signal pins, 4 spare pins, 34 power pins, and 34 ground pins. Of the 136

signal pins, 32 of them are multi–function and can be independently programmed either as IO ports or for an alternate standard/normal function.

As an IO port, any of these pins can be programmed as an input or output port, with the capability of generating a separate positive and

negative edge interrupt. See Section 2.3 for a summary of the multi–function IO ports versus their standard functions.

PIN #

NAME

TYPE

NAME AND FUNCTION

Memory Pins

D(31:0)

I/O

These pins are the data bus for the system. 8–bit SDRAMs should be connected to bits 7:0 and

16–bit SDRAMs and DRAMs should be connected to bits 15:0. All other 16–bit ports should be

connected to bits 31:16. Of course, 32–bit ports should be connected to bits 31:0. These pins are

normally outputs and only become inputs during reads, thus no resistors are required since the

bus will only float for a short period of time during bus turn–around.

A(12:0)

O

These pins are the address bus for the system. The address lines are multiplexed and can be

connected directly to SDRAM and DRAM devices. To generate the full 26–bit address for static

devices, an external latch must be used to latch the signals using the ALE signal. For static

devices, address bits 25:13 are provided by the external latch and address bits 12:0 (directly

connected from PR31100’s address bus) are held afterward by PR31100 processor for the

remainder of the address bus cycle.

168

ALE

O

This pin is used as the address latch enable to latch A(12:0) using an external latch, for generating

the upper address bits 25:13.

163

/RD

O

This pin is used as the read signal for static devices. This signal is asserted for reads from

/MCS3–0, /CS3–0, /CARD2CS and /CARD1CS for memory and attribute space, and for reads

from PR31100 processor accesses if SHOWPR31100 is enabled (for debugging purposes).

169

/WE

O

This pin is used as the write signal for the system. This signal is asserted for writes to /MCS3–0,

/CS3–0, /CARD2CS and /CARD1CS for memory and attribute space, and for writes to DRAM and

SDRAM.

199

/CAS0 (/WE0)

O

This pin is used as the CAS signal for SDRAMs, the CAS signal for D(7:0) for DRAMs, and the

write enable signal for D(7:0) for static devices.

198

/CAS1 (/WE1)

O

This pin is used as the CAS signal for D(15:8) for DRAMs and the write enable signal for D(15:8)

for static devices.

197

/CAS2 (/WE2)

O

This pin is used as the CAS signal for D(23:16) for DRAMs and the write enable signal for

D(23:16) for static devices.

195

/CAS3 (/WE3)

O

This pin is used as the CAS signal for D(31:24) for DRAMs and the write enable signal for

D(31:24) for static devices.

194

/RAS0

O

This pin is used as the RAS signal for SDRAMs and the RAS signal for Bank0 DRAMs.

193

/RAS1 (/DCS1)

O

This pin is used as the chip select signal for Bank1 SDRAMs and the RAS signal for Bank1

DRAMs.

192

/DCS0

O

This pin is used as the chip select signal for Bank0 SDRAMs.

202

DCKE

O

This pin is used as the clock enable for SDRAMs.

204

DCLKIN

I

This pin must be tied externally to the DCLKOUT signal and is used to match skew for the data

input when reading from SDRAM and DRAM devices.

205

DCLKOUT

O

This pin is the (nominal) 73.728 MHz clock for the SDRAMs.

207

DQMH

O

This pin is the upper data mask for a 16–bit SDRAM configuration.

208

DQML

O

This pin is the lower data mask for a 16–bit SDRAM or 8–bit SDRAM configuration.

124–126,

162

/CS3–0

O

These pins are the Chip Select 3 through 0 signals. They can be configured to support either

32–bit or 16–bit ports.

120–123

/MCS3–0

O

These pins are the MagicCard Chip Select 3 through 0 signals. They only support 16–bit ports.

106, 107

/CARD2CSH,L

O

These pins are the Chip Select signals for PCMCIA card slot 2.