PLS159 datasheet(1/12 Pages) PHILIPS

номер детали	PLS159

подробное описание детали	Programmable logic sequencer 16 횞 45 횞 12

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производитель	PHILIPS [NXP Semiconductors]

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Philips Semiconductors Programmable Logic Devices

Product specification

PLS159A

Programmable logic sequencer

(16

× 45 × 12)

25

October 22, 1993

853–1159 11164

DESCRIPTION

The PLS159A is a 3-State output, registered

logic element combining AND/OR gate arrays

with clocked J-K flip-flops. These J-K

flip-flops are dynamically convertible to

D-type via a “fold-back” inverting buffer and

control gate FC. It features 8 registered I/O

outputs (F) in conjunction with 4 bidirectional

I/O lines (B). These yield variable I/O gate

and register configurations via control gates

(D, L) ranging from 16 inputs to 12 outputs.

The AND/OR arrays consist of 32 logic AND

gates, 13 control AND gates, and 21 OR

gates with fusible link connections for

programming I/O polarity and direction. All

AND gates are linked to 4 inputs (I),

bidirectional I/O lines (B), internal flip-flop

outputs (Q), and Complement Array output

(C). The Complement Array consists of a

NOR gate optionally linked to all AND gates

for generating and propagating

complementary AND terms.

On-chip T/C buffers couple either True (I, B,

Q) or Complement (I, B, Q, C) input polarities

to all AND gates, whose outputs can be

optionally linked to all OR gates. Any of the

32 AND gates can drive bidirectional I/O lines

(B), whose output polarity is individually

programmable through a set of Ex-OR gates

for implementing AND-OR or AND-NOR logic

functions. Similarly, any of the 32 AND gates

can drive the J-K inputs of all flip-flops. There

are 4 AND gates for the Asynchronous

Preset/Reset functions.

All flip-flops are positive edge-triggered and

can be used as input, output or I/O (for

interfacing with a bidirectional data bus) in

conjunction with load control gates (L),

steering inputs (I), (B), (Q) and

programmable output select lines (E).

The PLS159A is field-programmable,

enabling the user to quickly generate custom

patterns using standard programming

equipment.

FEATURES

• High-speed version of PLS159

• f

MAX = 18MHz

– 25MHz clock rate

• Field-Programmable (Ni-Cr link)

• 4 dedicated inputs

• 13 control gates

• 32 AND gates

• 21 OR gates

• 45 product terms:

– 32 logic terms

– 13 control terms

• 4 bidirectional I/O lines

• 8 bidirectional registers

• J-K, T, or D-type flip-flops

• Power-on reset feature on all flip-flops

(Fn = 1)

• Asynchronous Preset/Reset

• Complement Array

• Active-High or -Low outputs

• Programmable OE control

• Positive edge-triggered clock

• Input loading: –100µA (max.)

• Power dissipation: 750mW (typ.)

• TTL compatible

• 3-State outputs

APPLICATIONS

• Random sequential logic

• Synchronous up/down counters

• Shift registers

• Bidirectional data buffers

• Timing function generators

• System controllers/synchronizers

• Priority encoder/registers

PIN CONFIGURATIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

N Package

CLK

I0

I1

I2

I3

B0

B1

B2

B3

F0

GND

F1

F2

F3

F4

F5

F6

F7

VCC

OE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A Package

F0

F1

F2

F3

F4

F5

F6

F7

VCC

OE

CLK

I0

I1

I2

I3

B0

B1

B2

B3 GND

N = Plastic Dual In-Line Package (300mil-wide)

A = Plastic Leaded Chip Carrier

ORDERING INFORMATION

DESCRIPTION

ORDER CODE

DRAWING NUMBER

20-Pin Plastic Dual In-Line Package (300mil-wide)

PLS159AN

0408D

20-Pin Plastic Leaded Chip Carrier

PLS159AA

0400E

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	PLS153AN	144Kb / 9P	Programmable logic arrays 18 횞 42 횞 10 October 22, 1993
	PLS153N	144Kb / 9P	Programmable logic arrays 18 횞 42 횞 10 October 22, 1993

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NXP Semiconductors	PLS100	127Kb / 8P	Programmable logic arrays 16 횞 48 횞 8 October 22, 1993
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