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LT1374CS8 датащи(PDF) 8 Page - Linear Technology |
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LT1374CS8 датащи(HTML) 8 Page - Linear Technology |
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8 / 32 page ![]() 8 LT1374 1374fb – + – + Σ INPUT 2.9V BIAS REGULATOR 500kHz OSCILLATOR FREQUENCY SHIFT CIRCUIT VSW FB VC LOCKOUT COMPARATOR GND 1374 BD SLOPE COMP 0.01 Ω BIAS* INTERNAL VCC CURRENT SENSE AMPLIFIER VOLTAGE GAIN = 20 SYNC SHDN SHUTDOWN COMPARATOR CURRENT COMPARATOR ERROR AMPLIFIER gm = 2000µMho FOLDBACK CURRENT LIMIT CLAMP BOOST RS FLIP-FLOP DRIVER CIRCUITRY S R 0.9V Q2 Q1 POWER SWITCH 2.42V 2.38V *BIAS PIN IS AVAILABLE ONLY ON THE S0-8 AND FE16 PACKAGES – + 0.4V 3.5 µA BLOCK DIAGRA APPLICATIO S I FOR ATIO FEEDBACK PIN FUNCTIONS The feedback (FB) pin on the LT1374 is used to set output voltage and provide several overload protection features. The first part of this section deals with selecting resistors to set output voltage and the remaining part talks about foldback frequency and current limiting created by the FB pin. Please read both parts before committing to a final design. The fixed 5V LT1374-5 has internal divider resis- tors and the FB pin is renamed SENSE, connected directly to the output. The suggested value for the output divider resistor (see Figure 2) from FB to ground (R2) is 5k or less, and a formula for R1 is shown below. The output voltage error caused by ignoring the input bias current on the FB pin is less than 0.25% with R2 = 5k. A table of standard 1% values is shown in Table 1 for common output voltages. Please read the following if divider resistors are increased above the suggested values. R RVOUT 1 22 42 242 = − () . . Table 1 OUTPUT R1 % ERROR AT OUTPUT VOLTAGE R2 (NEAREST 1%) DUE TO DISCREET 1% (V) (k Ω)(kΩ) RESISTOR STEPS 3 4.99 1.21 + 0.23 3.3 4.99 1.82 + 0.08 5 4.99 5.36 + 0.39 6 4.99 7.32 – 0.5 8 4.99 11.5 – 0.04 10 4.99 15.8 + 0.83 12 4.99 19.6 – 0.62 15 4.99 26.1 + 0.52 Figure 1. Block Diagram |
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