AD9865BCPRL datasheet(24/48 Pages) AD

24 / 48 page

AD9865

Rev. A | Page 24 of 48

Tx DIGITAL

FILTER

ADIO

[9:0]

OSCIN

RXEN

AD9865

FROM

Rx ADC

RXEN

TXEN

TXCLK

RXCLK

DAC_CLK

ADC_CLK

CLKOUT

DIGITAL ASIC

Tx/Rx

Data[9:0]

Figure 51. Example of a Half-Duplex Digital Interface

with AD9865 Serving as the Slave

Figure 52 shows a half-duplex interface with the AD9865 acting

as the master, generating all the required clocks. CLKOUT1

provides a clock equal to the bus data rate that is fed to the

ASIC as well as back to the TXCLK and RXCLK inputs. This

interface has the advantage of reducing the digital ASIC’s pin

count by three. The ASIC needs only to generate a bus control

signal that controls the data flow on the bidirectional bus.

Tx DIGITAL

FILTER

ADIO

[9:0]

Tx/Rx

Data[9:0]

CLKOUT1

AD9865

FROM

Rx ADC

RXEN

TXEN

BUS_CTR

TXCLK

RXCLK

CLKIN

DIGITAL ASIC

OSCIN

FROM

CRYSTAL

OR MASTER CLK

Figure 52. Example of a Half-Duplex Digital Interface

with AD9865 Serving as the Master

FULL-DUPLEX MODE

The full-duplex mode interface is selected when the MODE pin

is tied high. It can be used for full- or half-duplex applications.

The digital interface port is divided into two 6-bit ports called

Tx[5:0] and Rx[5:0], allowing simultaneous Tx and Rx opera-

tions for full-duplex applications. In half-duplex applications,

the Tx[5:0] port can also be used to provide a fast update of the

RxPGA (AD9875 backward-compatible) during an Rx opera-

tion. This feature is enabled by default and can be used to

reduce the required pin count of the ASIC (refer to RxPGA

Control section for details).

In either application, Tx and Rx data are transferred between

the ASIC and AD9865 in 6-bit (or 5-bit) nibbles at twice the

internal input/output word rates of the Tx interpolation filter

and ADC. Note that the TxDAC update rate must not be less

than the nibble rate. Therefore, the 2× or 4× interpolation filter

must be used with a full-duplex interface.

The AD9865 acts as the master, providing RXCLK as an output

clock that is used for the timing of both the Tx[5:0] and Rx[5:0]

ports. RXCLK always runs at the nibble rate and can be inverted

or disabled via an SPI register. Because RXCLK is derived from

the clock synthesizer, it remains active, provided that this func-

tional block remains powered on. A buffered version of the

signal appearing at OSCIN can also be directed to RXCLK by

setting Bit 2 of Register 0x05. This feature allows the AD9865 to

be completely powered down (including the clock synthesizer)

while serving as the master.

The Tx[5:0] port operates in the following manner with the SPI

are multiplexed together to form a 10-bit data-word in twos

complement format. The clock appearing on the RXCLK pin is

a buffered version of the internal clock used by the Tx[5:0]

port’s input latch with a frequency that is always twice the ADC

sample rate (2 × fADC). Data from the Tx[5:0] port is read on the

rising edge of this sampling clock, as illustrated in the timing

diagram shown in Figure 53. Note, TXQUIET must remain

high for the reconstructed Tx data to appear as an analog signal

at the output of the TxDAC or IAMP.

Tx2LSB

Tx0LSB

tDS

tDH

RXCLK

TXSYNC

Tx[5:0]

Tx1MSB

Tx1LSB

Tx2MSB

Tx3LSB

Tx3MSB

Figure 53. Tx[5:0] Port Full-Duplex Timing Diagram

The TXSYNC signal is used to indicate to which word a nibble

belongs. While TXSYNC is low, the first nibble of every word is

read as the most significant nibble. The second nibble of that

same word is read on the following TXSYNC high level as the

least significant nibble. If TXSYNC is low for more than one

clock cycle, the last transmit data is read continuously until

TXSYNC is brought high for the second nibble of a new trans-

mit word. This feature can be used to flush the interpolator

filters with zeros. Note that the GAIN signal must be kept low

during a Tx operation.

The Rx[5:0] port operates in the following manner with the SPI

are multiplexed together to form a 10-bit data-word in twos

complement format. The Rx data is valid on the rising edge of

RXCLK, as illustrated in the timing diagram shown in Figure 54.

The RXSYNC signal is used to indicate to which word a nibble

belongs. While RXSYNC is low, the first nibble of every word is

transmitted as the most significant nibble. The second nibble of

that same word is transmitted on the following RXSYNC high

level as the least significant nibble.

AD9865BCPRL датащи(PDF) 24 Page - Analog Devices

AD9865BCPRL датащи(HTML) 24 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL