AD9865BCPRL datasheet(19/48 Pages) AD

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AD9865

Rev. A | Page 19 of 48

SERIAL PORT

Table 10. SPI Register Mapping

Power-Up Default Value

MODE = 0 (Half-Duplex)

MODE = 1 (Full-Duplex)

Address

(Hex)1

Bit

Break-

down

Description

Width

CONFIG = 0

CONFIG = 1

CONFIG = 0

CONFIG = 1

Comments

SPI PORT CONFIGURATION AND SOFTWARE RESET

0x00

(7)

4-Wire SPI

(6)

LSB First

(5)

S/W Reset

Default SPI configuration is

3-wire, MSB first.

POWER CONTROL REGISTERS (via PWR_DWN pin)

0x01

(7)

Clock Syn.

(6)

TxDAC/IAMP

(5)

Tx Digital

(4)

REF

(3)

ADC CML

(2)

ADC

(1)

PGA Bias

(0)

RxPGA

PWR_DWN = 0.

Default setting is for all

blocks powered on.

0x02

(7)

CLK Syn.

(6)

TxDAC/IAMP

(5)

Tx Digital

(4)

REF

(3)

ADC CML

(2)

ADC

(1)

PGA Bias

(0)

RxPGA

PWR_DWN = 1.

Default setting* is for all

functional blocks powered

down except PLL.

*MODE = CONFIG = 1.

Setting has PLL powered

down with OSCIN input

routed to RXCLK output.

HALF-DUPLEX POWER CONTROL

0x03

(7:3)

Tx OFF Delay

(2)

Rx _TXEN

(1)

Tx PWRDN

(0)

Rx PWRDN

0xFF

N/A

Default setting is for TXEN

input to control power

on/off of Tx/Rx path.

Tx driver delayed by 31

1/fDATA clock cycles.

PLL CLOCK MULTIPLIER/SYNTHESIZER CONTROL

0x04

(5)

Duty Cycle Enable

(4)

fADC from PLL

(3:2)

PLL Divide-N

(1:0)

PLL Multiplier-M

10*

Default setting is Duty Cycle

Restore disabled, ADC CLK

from OSCIN input, and PLL

multiplier × 2 setting.

*PLL multiplier × 4 setting.

0x05

(2)

OSCIN to RXCLK

(1)

Invert RXCLK

(0)

Disabled RXCLK

Full-duplex RXCLK normally

at nibble rate.

*Exception on power-up.

0x06

(7:6)

CLKOUT2 Divide

(5)

CLKOUT2 Invert

(4)

CLKOUT2 Disable

(3:2)

CLKOUT1 Divide

(1)

CLKOUT1 Invert

(0)

CLKOUT1 Disable

Default setting is CLKOUT2

and CLKOUT1 enabled with

divide-by-2.

*CLKOUT1 and CLKOUT2

disabled.

Rx PATH CONTROL

0x07

(5)

Initiate Offset Cal.

(4)

Rx Low Power

(0)

Rx Filter ON

Default setting has LPF ON

and Rx path at nominal

power bias setting.

*Rx path to low power.

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