AD9865BCPRL datasheet(23/48 Pages) AD

23 / 48 page

AD9865

Rev. A | Page 23 of 48

DIGITAL INTERFACE

The digital interface port is configurable for half-duplex or full-

duplex operation by pin-strapping the MODE pin low or high,

respectively. In half-duplex mode, the digital interface port

becomes a 10-bit bidirectional bus called the ADIO port. In

full-duplex mode, the digital interface port is divided into two

6-bit ports called Tx[5:0] and Rx[5:0] for simultaneous Tx and

Rx operations. In this mode, data is transferred between the

ASIC and AD9865 in 6-bit (or 5-bit) nibbles. The AD9865 also

features a flexible digital interface for updating the RxPGA and

TxPGA gain registers via a 6-bit PGA port or Tx[5:0] port for

fast updates, or via the SPI port for slower updates. See the

RxPGA Control section for more information.

HALF-DUPLEX MODE

The half-duplex mode functions as follows when the MODE

pin is tied low. The bidirectional ADIO port is typically shared

in burst fashion between the transmit path and receive path.

Two control signals, TXEN and RXEN, from a DSP (or digital

ASIC) control the bus direction by enabling the ADIO port’s

input latch and output driver, respectively. Two clock signals are

also used: TXCLK to latch the Tx input data, and RXCLK to

clock the Rx output data. The ADIO port can also be disabled

by setting TXEN and RXEN low (default setting), thus allowing

it to be connected to a shared bus.

Internally, the ADIO port consists of an input latch for the Tx

path in parallel with an output latch with three-state outputs for

the Rx path. TXEN is used to enable the input latch; RXEN is

used to three-state the output latch. A five-sample-deep FIFO is

used on the Tx and Rx paths to absorb any phase difference be-

tween the AD9865’s internal clocks and the externally supplied

clocks (TXCLK, RXCLK). The ADIO bus accepts input data-

words into the transmit path when the TXEN pin is high, the

RXEN pin is low, and a clock is present on the TXCLK pin, as

shown in Figure 49.

TXCLK

TXEN

ADIO[9:0]

RXEN

TX0

TX2

TX3

TX4

TX1

tDIS

tDH

tEN

tDS

Figure 49. Transmit Data Input Timing Diagram

The Tx interpolation filter(s) following the ADIO port can be

flushed with zeros, if the clock signal into the TXCLK pin is

present for 33 clock cycles after TXEN goes low. Note that the

data on the ADIO bus is irrelevant over this interval.

The output from the receive path is driven onto the ADIO bus

when the RXEN pin is high, and a clock is present on the RXCLK

pin. While the output latch is enabled by RXEN, valid data

appears on the bus after a 6-clock-cycle delay due to the internal

FIFO delay. Note that Rx data is not latched back into the Tx

path, if TXEN is high during this interval with TXCLK present.

The ADIO bus becomes three-stated once the RXEN pin returns

low. Figure 50 shows the receive path output timing.

tPZL

RXEN

ADIO[9:0]

RXCLK

tVT

tPLZ

tOD

RX0

RX1

RX2

RX3

Figure 50. Receive Data Output Timing Diagram

To add flexibility to the digital interface port, several program-

ming options are available in the SPI registers. These options

are listed in Table 13. The default Tx and Rx data input formats

are straight binary, but can be changed to twos complement.

The default TXEN and RXEN settings are active high, but can

be set to opposite polarities, thus allowing them to share the

same control. In this case, the ADIO port can still be placed

onto a shared bus by disabling its input latch via the control

signal, and disabling the output driver via the SPI register. The

clock timing can be independently changed on the transmit and

receive paths by selecting either the rising or falling clock edge

as the validating/sampling edge of the clock. Lastly, the output

driver’s strength can be reduced for lower data rate applications.

Table 13. SPI Registers for Half-Duplex Interface

Address (Hex)

Bit

Description

0x0C

(4)

Invert TXEN

(1)

TXCLK negative edge

(0)

Twos complement

0x0D

(5)

Rx port three-state

(4)

Invert RXEN

(1)

RXCLK negative edge

(0)

Twos complement

0x0E

(7)

Low digital drive strength

The half-duplex interface can be configured to act as a slave or a

master to the digital ASIC. An example of a slave configuration

is shown in Figure 51. In this example, the AD9865 accepts all

the clock and control signals from the digital ASIC. Because the

sampling clocks for the DAC and ADC are derived internally

from the OSCIN signal, the TXCLK and RXCLK signals must

be at exactly the same frequency as the OSCIN signal. The

phase relationships among the TXCLK, RXCLK, and OSCIN

signals can be arbitrary. If the digital ASIC cannot provide a low

jitter clock source to OSCIN, use the AD9865 to generate the

clock for its DAC and ADC, and to pass the desired clock signal

to the digital ASIC via CLKOUT1 or CLKOUT2.

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