MPC8313ECVRAFF datasheet(81/88 Pages) FREESCALE

81 / 88 page

MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

System Design Information

20.3.1

Experimental Determination of the Junction Temperature with a

Heat Sink

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the

interface between the case of the package and the interface material. A clearance slot or hole is normally

required in the heat sink. Minimizing the size of the clearance is important to minimize the change in

thermal performance caused by removing part of the thermal interface to the heat sink. Because of the

experimental difficulties with this technique, many engineers measure the heat sink temperature and then

back calculate the case temperature using a separate measurement of the thermal resistance of the

interface. From this case temperature, the junction temperature is determined from the junction to case

thermal resistance.

TJ = TC + (RθJC x PD)

Where:

TJ = junction temperature (°C)

TC = case temperature of the package

RθJC = junction-to-case thermal resistance

PD = power dissipation

21 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC8313E SYS_CLK_IN

21.1

System Clocking

The MPC8313E includes two PLLs.

1. The platform PLL (AVDD2) generates the platform clock from the externally supplied

SYS_CLK_IN input in PCI host mode or SYS_CLK_IN/PCI_SYNC_IN in PCI agent mode. The

frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL ratio

configuration bits as described in Section 19.1, “System PLL Configuration.”

2. The e300 Core PLL (AVDD1) generates the core clock as a slave to the platform clock. The

frequency ratio between the e300 core clock and the platform clock is selected using the e300

PLL ratio configuration bits as described in Section 19.2, “Core PLL Configuration.”

21.2

PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1,

AVDD2 respectively). The AVDD level should always be equivalent to VDD, and preferably these voltages

will be derived directly from VDD through a low frequency filter scheme such as the following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to

provide five independent filter circuits as illustrated in Figure 40, one to each of the five AVDD pins. By

providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the

other is reduced.

MPC8313ECVRAFF датащи(PDF) 81 Page - Freescale Semiconductor, Inc

MPC8313ECVRAFF датащи(HTML) 81 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

датащи скачать

ссылки URL