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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8313ECVRAFF датащи(PDF) 73 Page - Freescale Semiconductor, Inc |
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MPC8313ECVRAFF датащи(HTML) 73 Page - Freescale Semiconductor, Inc |
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73 / 88 page  MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 73 Clocking 19.2 Core PLL Configuration RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 60 shows the encodings for RCWL[COREPLL]. COREPLL values that are not listed in Table 60 should be considered as reserved. NOTE Core VCO frequency = Core frequency × VCO divider VCO divider has to be set properly so that the core VCO frequency is in the range of 400–800 MHz. Low 0101 5 : 1 120 125 167 Low 0110 6 : 1 144 150 1 CFG_CLKIN_DIV select the ratio between SYS_CLK_IN and PCI_SYNC_OUT. 2 SYS_CLK_IN is the input clock in host mode; PCI_CLK is the input clock in agent mode. Table 60. e300 Core PLL Configuration RCWL[COREPLL] core_clk : csb_clk Ratio VCO divider 1 0–1 2–5 6 nn 0000 0 PLL bypassed (PLL off, csb_clk clocks core directly) PLL bypassed (PLL off, csb_clk clocks core directly) 11 nnnn nn/a n/a 00 0001 01:1 2 01 0001 01:1 4 10 0001 01:1 8 00 0001 11.5:1 2 01 0001 11.5:1 4 10 0001 11.5:1 8 00 0010 02:1 2 01 0010 02:1 4 10 0010 02:1 8 00 0010 12.5:1 2 01 0010 12.5:1 4 Table 59. CSB Frequency Options (continued) CFG_CLKIN_DIV at reset 1 SPMF csb_clk : Input Clock Ratio 2 Input Clock Frequency(MHz)2 24 25 33.33 66.67 csb_clk Frequency(MHz) |
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