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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMG3992 датащи(PDF) 47 Page - OSRAM GmbH |
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TMG3992 датащи(HTML) 47 Page - OSRAM GmbH |
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47 / 96 page  Page 46 ams Datasheet Document Feedback [v1-06] 2018-Feb-27 TMG3992 − Register Description RAM Registers (0x00 - 0x7F) Pattern RAM Integrated RAM provides 128 bytes of bit-pattern data storage which defines the activation state of the LDR pin (LED ON/OFF) during burst event. After the device receives a “start burst com- mand”, each bit of RAM sets the state of the LDR pin for a time period defined by the timing register values. Bits are burst out of the LDR pin MSB first starting at address 0x00. RAM can be accessed (read or write) a byte at a time or in pages of any length. RAM cannot be accessed while PON=0 or if a pattern is actively transmitting. RAM content is persistent as long as VDD is present on the device. The RAM is also used for gesture FIFO storage. As a result, when the gesture engine becomes enabled the pattern RAM will be overwritten. Figure 45: RAM Registers 765 432 1 0 NIBBLE0 NIBBLE1 Field Bits Description NIBBLE0 7:4 First 4-bits of bit-pattern generated. Burst bit 7 to bit 4. NIBBLE1 3:0 Second 4-bits of bit-pattern generated. Burst bit 3 to bit 0. |
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