TMG3992 datasheet(41/96 Pages) OSRAM

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[v1-06] 2018-Feb-27

TMG3992 − Detailed Description

Upon enabling the Pattern Burst engine, PON=PBEN=1, the

IDLE state is entered. In this state, control of the LDR pin is re-

moved from the Proximity/Gesture modules and is exclusively

driven by the pattern stored in RAM. IR pattern emission begins

when any value is written to CONFIG_A7, Symbol Length/Start

Transmission register, ISLEN, or whenever PBEN bit transitions

from 0 to 1. Prior to writing ISLEN or enabling PBEN bit control

registers and pattern RAM must be valid (previously

programmed).

Pattern data stored in the128-byte RAM defines the activation

state of the LDR pin (LED ON/OFF) during an IRBeam Symbol

burst event. After ISLEN is written each bit of RAM sets the state

of the LDR pin with a pulse width set by bit-time control bits,

IBT, located in CONFIG_A6. Bits are burst out of the LDR pin MSB

first starting at address 0x00. Each integer value placed in ISLEN

ample, if ISLEN = 0, the first four bits of address 0x00 (bits: 7, 6,

5, and 4) modulate the LDR current.

Immediately after writing the ISLEN, the PBUSY bit is set and a

Burst Symbol event commences. During this event the LDR pin

modulates LED current, bursting the bit-wise (Barcode symbol)

pattern stored in RAM starting at location 0x00. Refer to

Figure 41, Figure 42, and Figure 43 for a graphical representa-

tion of how the a complete pattern burst is built using the RAM

and control register settings. The control register for bit-time,

IBT, provides a wide range of timing options to satisfy require-

ments set by commonly used barcode standards. Equations for

Bit Time, IBT, and other timing parameters are located in the

By setting a non-zero value in the Symbol Number of Loops

executed for each write to ISLEN. Between Symbols the LDR pin

is turned OFF for a period of time defined by the Symbol LDR

OFF Delay register, ISOFF. This sequence of symbol transmission

followed by an LDR OFF Delay, ISOFF, represents a Symbol Loop

event, as depicted in Figure 42. A maximum of 256 symbol loops

can be executed. After the final loop has completed the Packet

Loop event commences.

A Packet Loop event, as depicted in Figure 43, is much like a

Symbol Loop event except that inside a packet loop a number

of entire Symbol Loop events are repeated. By setting a non-ze-

ro value in the Packet Number of Loops Register, IPNL, more

than one packet loop event can be executed for each write to

ISLEN. Between packets the LDR pin is turned OFF for a period

of time as defined by the Packet LDR OFF Delay register, IPOFF.

A minimum setting of 0 in IPNL prevents any additional packet

loops from running; however, a packet LDR OFF delay always

runs at least one time. A maximum of 256 Packet loops can be

executed. After the final loop has completed, interrupts are as-

serted, PBUSY is cleared, and control is passed back to the IDLE

state.

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