TMF8805 datasheet(23/74 Pages) OSRAM

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TMF8805

Datasheet

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DS000692

• v7-00 • 2023-Dec-01

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6.1.4

ENABLE register (Address 0xE0)

Table 15: ENABLE register

Addr: 0xE0

ENABLE

Field

Name

Rst

Type

Description

cpu_reset

RW_SC

Write a '1' here to reset CPU. This generates global reset, fully

resetting CPU and all CPU registers. The bit resets itself, no need to

explicitly clear it.

cpu_ready

CPU is ready to handle I²C - if this bit is zero, then only the registers

0xe0 and above are usable, the memory mapped I²C space is not

used.

Bit gets set only explicitly by software, therefore a functional and

running firmware is necessary for this bit to work.

pon

R_PUSH

1=Activate oscillator; 0=Ask CPU to go to standby

Activating the oscillator is implemented in hardware. Whenever this

and CPU receives a PON1 interrupt. It is implemented in the

bootloader to execute a reset at this point, but the application goes to

an IDLE state.

De-activating the oscillator is a software assisted process. It is

important that the CPU powers down all modules properly before

turning off the oscillator, therefore this is implemented in firmware. So

writing a '0' to this register will trigger an internal CPU interrupt. The

firmware, after powering down everything, sets the device into standby

state.

6.1.5

INT_STATUS register (Address 0xE1)

Table 16: INT_STATUS register

Addr: 0xE1

INT_STATUS

Field

Name

Rst

Type

Description

int2

R_PUSH1

Raw histogram available interrupt for App0; asserted when a raw

histogram can be retrieved from I²C.

int2 status. If bit is asserted, and int2_enab is asserted as well, then the

INT pin will be pulled low. Writing a '1' here will clear int1 condition.

int1

R_PUSH1

Object detection interrupt for App0; asserted when a result from object

detection is available.

int1 status. If bit is asserted, and int1_enab is asserted as well, then the

INT pin will be pulled low. Writing a '1' here will clear int1 condition.

Note: An interrupt is raised on every result from object detection including

no-target unless persistence is set > 0

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