TCS34005FN datasheet(15/35 Pages) OSRAM

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Page 14

Datasheet, Public

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[v2-00] 2023-Feb-09

TCS3400 − Register Description

Enable Register (ENABLE 0 x 80)

The Enable Register is used primarily to power the device

ON/OFF, and enable functions and interrupts.

Figure 20:

Enable Register

0x9A

BDATAL

Blue ADC low data register

0x00

0x9B

BDATAH

Blue ADC high data register

0x00

0xC0

R/W

Access IR Channel

0x00

0xE4

IFORCE

Force Interrupt

0x00

0xE6

CICLEAR

Clear channel interrupt clear

0x00

0xE7

AICLEAR

Clear all interrupts

0x00

Reserved

SAI

Reserved

AIEN

WEN

Reserved

AEN

PON

Field

Bits

Description

Reserved

Reserved. Write as 0.

SAI

Sleep After Interrupt. When asserted, the device will power down at the end

of a RGBC cycle if an interrupt is generated.

Reserved

Reserved. Write as 0.

AIEN

ALS Interrupt Enable. When asserted permits ALS interrupts to be generated,

subject to the persist filter.

WEN

Wait Enable. This bit activates the wait feature. Writing a 1 activates the wait

timer. Writing a 0 disables the wait timer.

Reserved

Reserved. Write as 0.

AEN

ADC Enable. This bit activates the four-channel (RGBC) ADC. Writing a 1

enables the ADC. Writing a 0 disables the ADC.

PON

Power ON. This bit activates the internal oscillator to permit the timers and

ADC channels to operate. Writing a 1 activates the oscillator. Writing a 0

disables the oscillator and puts the part into a low power sleep mode. During

reads and writes over the I²C interface, this bit is temporarily overridden and

the oscillator is enabled, independent of the state of PON.

Address

Name

R/W

Reset Value

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