AVR32AP datasheet(29/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

In the second code, mtsr writes the new value of JOSP as it leaves A1. As the add instruction

needs JOSP to be updated when it enters ID because of the register remapping, two nop

instructions must be inserted.

ssrf R

incjosp

-2

add

r0, r0

ssrf R

mfsr r8, JOSP

sub

r8, 2

mtsr JOSP, r8

nop

add

r0, r0

3.9.4

Execution of TLB instructions

The TLB instructions tlbr, tlbw and tlbs are used to maintain the data in the TLB. They use the

TCB bus to access the MMU, and the instruction is dispatched to the MMU when the instruction

is in the D pipeline stage. The programmer must make sure that any writes to the TLB with the

tlbw instructions are completed before the TLB entry is used in an icache or dcache memory

access. This is handled automatically for any dcache memory access, since any load/store

instructions flow through the same pipeline as the tlbw instruction, and the tlbw instruction will

have left the D stage before any load/store instruction enters it. Any icache access that is to use

the page table entry written by tlbw must wait until the tlbw instruction is in the D pipeline stage.

This may require inserting a nop or another unrelated instruction, as illustrated in the code

below, which shows a part of a ITLB miss handler. The rete instruction wishes to use the page

table entry written by tlbw to generate the physical address of the instruction to return to.

tlbw

nop

rete

3.9.5

Execution of cache instructions

The cache instruction perform various cache-relatated operations, like invalidation of lines.

Some of these operations are harmless, and need no sequencing or hazard consideration.

Other operations, like invalidation, require more concern. The programmer must make sure that

any invalidation is committed before any instruction the depends on the invalidation already

being performed is allowed to execute.

The cache instruction use the TCB bus to access the caches, and the instruction is dispatched

to the caches when the instruction is in the D pipeline stage. The programmer must make sure

that any cache instructions are completed before any icache or dcache memory access that

depends on the cache instruction is executed. This is handled automatically for any dcache

memory access, since any load/store instructions flow through the same pipeline as the cache

instruction, and the cache instruction will have left the D stage before any load/store instruction

enters it. Any icache access that is dependent on the cache instruction must wait until the cache

instruction is in the D pipeline stage. This may require inserting a nop or another unrelated

instruction, as illustrated in the code below. The rjmp instruction wishes to jump to a location

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