AVR32AP datasheet(23/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

3.5

Multiply pipeline

All multiply instructions execute in the multiply pipeline. This pipeline contains a 32 by 16 multi-

plier array, and 16x16 and 32x16 multiplications therefore have an issue latency of one cycle.

Multiplication of 32 by 32 bits require two iterations through the multiplier array, and therefore

needs several cycles to complete. Additional cycles may be needed if an accumulation is to be

performed. This will stall the multiply pipeline until the instruction is complete.

A special accumulator cache is implemented in the MUL pipeline. This cache saves the multiply-

accumulate result in dedicated registers in the MUL pipeline, as well as writing them back to the

cache, instead of from the register file. This will speed up MAC operations by one clock cycle. If

a MAC instruction targets a register not found in the cache, one clock cycle is added to the MAC

operation, loading the accumulator value from the register file into the cache. In the next cycle,

the MAC operation is restarted automatically by hardware. If a multiply (not MAC) instruction is

executed with target address equal to that of a valid cached register, the multiply instruction will

update the cache. All multiply and divide instructions will update the cache with its result, so that

a subsequent MAC to the same register will not have to preload the cache.

The accumulator cache can hold one doubleword accumulator value, or one word accumulator

value. Hardware ensures that the accumulator cache is kept consistent. If another pipeline

updates one of the registers kept in the accumulator cache, the cache is invalidated. The cache

is automatically invalidated after reset.

Some of the multiply instructions, machh.d, macwh.d, mulwh.d and mulnwh.d, produce a 48-bit

result that is to be placed in two registers. These instructions all have an issue latency of 1, even

though the MUL pipe only has one writeback port and two results are produced. This is handled

by delaying the writeback of the low register until the MUL pipeline is idle. Then, the low register

can be written back without stalling the MUL pipe. The high register is written back to the register

file when the instruction leaves the M2 stage. This scheme allows several of these instructions to

be issued consecutively, with no stalls due to writeback port congestion. This will increase per-

formance in MUL-intensive applications such as DSP algorithms. The MUL pipe can only hold

one delayed register for writeback, so a MUL instruction writing to another register will have to

stall one cycle in IS if a writeback is pending in the MUL pipe. Hazard detection is performed on

the pending writeback register, so any instruction reading a register pending writeback will stall

in IS until the value is forwardable in M2.

The multiply pipeline also contains a divider, performing multicycle 32-by-32 signed and

unsigned division with both quotient and remainder outputs.

In general, the MUL instructions do not set any flags. However, some of the MUL instructions

may set the saturate (Q) flag. No hazard detection is performed on this setting of the Q flag. The

programmer must ensure that such a Q flag update has propagated to the status register

before using the Q flag.

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