AVR32AP datasheet(83/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

requirements of the TCB bus must be obeyed. This may require stalling of the LS pipeline for the

required number of clock cycles.

8.4.1

Stalling of the TCB bus and the LS pipeline

An addressed TCB slave may stall the TCB bus and the LS pipeline if it is unable to fulfill the

required TCB timing. The addressed slave can perform this stalling by outputting a logical-0

value on its tcb_ready output. Writing a value of zero on tcb_ready will cause the LS pipeline

and the data cache to stall until tcb_ready is written to one again. When the CPU LS pipeline

stalls, all outputs from the CPU to the TCB bus will remain unchanged.

If the CPU LS pipeline stalls for some reason, the TCB may need to be informed if the LS stall

affects a TCB transfer. The tcb_cpustalled signal is a registered version of the stall signal in the

LS pipeline. If the CPU was stalled in the previous cycle, tcb_cpustalled is asserted. Otherwise,

tcb_cpustalled is disasserted. Since disassertion of tcb_ready will cause the LS pipeline to stall,

tcb_cpustalled will always be high the cycle following a cycle where tcb_ready was low.

8.4.2

Coprocessor operation

The cop instruction issues a command in the form of an opcode and three operand addresses to

the addressed coprocessor. The coprocessor operation only uses the address phase of the bus

transaction, while the data phase is unused and all signals are considered don’t care.

If the CPU stalls immediately after issuing a coprocessor operation, a coprocessor operation

opcode will be present on tcb_cmd for multiple cycles. If the TCB slave needs to avoid the oper-

ation being executed several times, the TCB slave must qualify any coprocessor operation

opcodes with tcb_cpustalled being low.

8.4.3

Writing data to coprocessor

There are several instructions that transfer data to coprocessors. These instructions are: ldc.d,

ldc.w, ldcm.d, ldcm.w, mvrc, mtdr and mtsr. Mtdr and mtsr are not coprocessor instructions, but

use the TCB in a manner very similar to mvrc, and is therefore included here. Data can be trans-

ferred to coprocessor registers in sizes of word and doubleword. The data transferred to the

coprocessor register file is either read from memory or from one of the integer registers in the

CPU.

The ldcm instructions behave similarly to the ldm and popm instructions. The hardware always

try to transfer a doubleword from the cache in order to speed up the data transfer. This is suc-

cessful if the memory pointer is doubleword aligned. Otherwise, a word access is performed

first, then the remaining transfers are performed as doubleword accesses.

The FSM in the DA stage decomposes load of multiple registers into a sequence of load of

words and doublewords. These accesses are pipelined according to the TCB rules, allowing a

bus transfer of word or doubleword per clock cycle.

If the CPU stalls after issuing a TCB write command, tcb_wdataa and tcb_wdatab will contain

the write data for the previous TCB bus cycle. This write data will be present on the bus until the

last cycle where tcb_cpustalled is high. In this cycle, the write data for the stalled TCB write com-

mand will be present on the bus. If the TCB slave needs to avoid that the write data for the

previous TCB command is written to the TCB slave destination registers for the stalled (current)

write, the TCB slave must not update the TCB destination registers when tcb_cpustalled is high.

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