VT6103 datasheet(13/46 Pages) VIA

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VT6103 - Fast Ethernet 10 / 100 PHY / Transceiver

Revision 1.1 April 15, 2002

-7-

Technologies, Inc.

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REGISTERS

The VT6103 internal register set consists of thirty-two 16-bit

MI (Management Interface) registers (of which 9 registers are

currently undefined / reserved).

The bits of PHY registers 0-8 are defined by the IEEE 802.3u

standard. The remaining PHY registers have vendor specific

bit definitions. All register bits implemented by the VT6103

are described in this data sheet (see register summary table

below, bit summary table on the next page, and detailed

PHY registers are addressed by the MAC by sending register

address pointer information via the MI interface (serially over

the MDIO pin clocked by MDC) with register read / write

data transfer via the same pins. For more information on this

mechanism, refer to IEEE 802.3 section 22.2.4.

In the register descriptions that follow, the following

abbreviations are used:

RW = Read / Write

RO = Read Only

SC = Self Clearing

LH = Latch High

LL = Latch Low

“Self Clearing” bits are normally 0.

If set to 1 they will

perform the indicated function then automatically be cleared

back to 0 by the chip. “Latch High” and “Latch Low” bits are

used to record that an event (level) occurred. For Latch High

bits, if the bit ever goes high, it will latch at that high level

until read (the read will clear the bit). For “Latch Low” bits,

if the bit goes low, it will stay at a low level until read (the

read will set the bit high).

Table 3. Register Summary

Offset

Offset Management Interface Registers

Bits Default Acc Page

00h

Management Interface Control

3100h RW

00h

Management Interface Status

7849h RO

01h

PHY Identifier 0

0101h RO

02h

PHY Identifier 1

8F20h RO

03h

Auto-Negotiation Advertisement Base

05E1h RW

04h

Link Partner Advertisement Base

0000h RO

05h

Auto-Negotiation Expansion

0004h RO

06h

Auto-Negotiation Advertisement Next

2001h RW

07h

Link Partner Advertisement Next

0000h RO

9-15

09-0Fh -reserved-

—

10h

PHY Configuration 1

0800h RW

11h

PHY Configuration 2

F7FFh RW

12h

PHY Configuration 3

0800h RW

13h

PHY Configuration 4

FFFCh RW

14h

PHY Status

0000h RO

15h

Link Fail Counter

0000h RO

16h

Invalid Symbol / Jabber Error Counter

0000h

17h

False Carrier / SQE Counter

0000h RO

24-25

18-19h -reserved-

—

1Ah

PHY Test Configuration 1

0012h RW

1Bh

PHY Test Configuration 2

C500h RW

1Ch

PHY Test Configuration 3

0208h RW

1Dh

PHY Test Configuration 4

0030h RW

1Eh

PHY Test Configuration 5

001Bh RW

1Fh

PHY Test Configuration 6

0000h RW

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