VT6103 datasheet(21/46 Pages) VIA

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VT6103 - Fast Ethernet 10 / 100 PHY / Transceiver

Revision 1.1 April 15, 2002

-15-

Technologies, Inc.

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Offset 28 (1Ch) – PHY Test Configuration 3 (0208h) ...RW

Hold DPLL Phase Setting

Disable ...................................................default

Enable

14-10 DPLL Clock Phase Setting...................... default = 0

9-8

DPLL Low Pass Filter Bandwidth ..... default = 10b

Output DPLL Recovered Clock Phase to PHY

Disable ...................................................default

Enable

PHY Set DPLL Phase Capability

Disable ...................................................default

Enable

DPLL Loopback Mode

Disable ...................................................default

Enable

Rd100, Rd10 Output to PHY

Disable ...................................................default

Enable

Slew Rate Control for 100 Transmitter

0Disable

Enable ...................................................default

Baseline Wander Correction

Disable ...................................................default

Enable

Equalizer Peak Detector Scheme Control Using

Value in Bit-0

Disable ...................................................default

Enable

Control Equalizer Peak Detector Scheme ... def = 0

Offset 29 (1Dh) – PHY Test Configuration 4 (0030h) ... RW

Hold Adeq Operation, Keep Current Equalizer

Gain Setting

Disable................................................... default

Enable

14-9 Adeq Gain Amount Setting ..................... default = 0

Adeq Can Output Gain Setting

Disable................................................... default

Enable

PHY Can Set Adeq Gain Amount

Disable................................................... default

Enable

6-5

Adeq Low Pass Filter Bandwidth ....... default = 01b

Adeq Test Buffers AOP1/AON1, AOP2/AON2

0Disable

Enable................................................... default

3-2

Adeq

Clock

Setting

for 100BaseT Adaptive

Equalizer

.............................................. default = 0

Bypass 10BaseT Receiver Filter

Disable................................................... default

Enable

Mask Sqh10m and Sq110m in Test Mode

Disable................................................... default

Enable

Offset 30 (1Eh) – PHY Test Configuration 5 (001Bh) .. RW

15-14 Fx Mode Transmitter Current Source Control,

10BaseT Transmitter Output Slew Rate Control

.......................................... default = 00b

13-12 10BaseT Pre-Emphasis Control.......... default = 00b

11-10 Control Attenuator Attenuation Factor,

100 Transmitter Output Amplitude ... default = 00b

9-8

100BaseT Programmable Select Clock Phase to

Latch Transmit Data ........................... default = 00b

7-6

10BaseT Transmitter Output Signal Amplitude

.......................................... default = 00b

5-3

ADEQ Peak Detector Reference Peak Select

........................................ default = 011b

2-0

ADEQ Slicer Threshold Level Select

........................................ default = 011b

Offset 31 (1Fh) – PHY Test Configuration 6 (0000h) ... RW

15-10 Select Signal Output to LED Pins........... default = 0

9-5

Select Signal Output to MII Pins ............ default = 0

Speedup Flags in NwayTxSm.................. default = 0

Speedup Tx10Flag in TxAct10................ default = 0

Speedup NLPMaxFlag in Timer............. default = 0

Speedup NLPMinFlag in Timer ............. default = 0

Speedup StabFlag in MLTStatus............ default = 0

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