VT6103 datasheet(10/46 Pages) VIA

10 / 46 page

VT6103 - Fast Ethernet 10 / 100 PHY / Transceiver

Revision 1.1, April 15, 2002

-4-

Pin Descriptions

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Pin Descriptions

Table 2. Pin Descriptions

Management Interface (MI)

Signal Name

Pin #

I/O

Signal Description

MDIO

1IO

Management Interface (MI) Data I/O. Received from the external MAC.

MDC

Management Interface (MI) Clock.

Received from the external MAC as a timing

reference for MDIO

INT# / PHYAD0

Management Interface (MI) Interrupt Out. Active low.

Media Independent Interface (MII)

Signal Name

Pin #

I/O

Signal Description

RXC

Receive Clock.

Timing reference for transfer of RXD and RXDV.

25 MHz when

operating at 100 Mbps and 2.5 MHz when operating at 10 Mbps (always active).

RXD3 / PHYAD1,

RXD2 / PHYAD2,

RXD1 / PHYAD3,

RXD0 / PHYAD4

Receive Data. These bits transition with RXC. RXD[3:0] should accepted by the external

MAC for each RXC period in which RXDV is asserted. RXD0 is the least significant bit.

While RXDV is de-asserted, RXD[3:0] have no effect upon the switch’s MAC and the

value of RXD[3:0] is unspecified.

RXDV / BYPOSC

Receive Data Valid. RXDV is driven to indicate that nibbles are being presented on the

MII for receiving. RXDV transitions synchronous to RXC. It is asserted synchronously

with the first nibble of the preamble and remains asserted while all nibbles to be received

are presented to the MII.

RXER /ISO

Receive Error. The VT6103 asserts this output when it receives invalid symbols from the

network

TXC

Transmit Clock.

Timing reference for transfer of TXD and TXEN.

25MHz when

operating at 100 Mbps and 2.5 MHz when operating at 10 Mbps (always active).

TXD[3-0]

20, 19,

18, 17

Transmit Data. These bits transition relative to TXC. TXD[3:0] are accepted from the

external MAC for each TXC period in which TXEN is asserted.

TXD0 is the least

significant bit. While TXEN is de-asserted, TXD[3:0] have no effect and the value of

TXD[3:0] is unspecified.

TXEN

Transmit Enable.

Indicates transmit active from the MII port.

TXEN transitions

synchronous to TXC. TXEN indicates that the nibbles presented on TXD[3-0] are valid

for transmission. TXEN is asserted synchronously with the first nibble of the preamble

and remains asserted while all nibbles to be transmitted are presented to the MII interface.

TXER

Transmit Error. The MAC asserts this input when an error has occurred in the input

stream.

COL /SYMB

Collision Detect. Asserted asynchronously upon detection of a collision on the medium

and remains asserted while the collision condition persists.

CRS /RPTR

Carrier Sense. Asserted asynchronously upon detection of a non-idle medium or while

TXEN is asserted. Deasserted asynchronously upon detection of idle conditions on both

transmit and receive media.

Remains asserted throughout the duration of a collision

condition.

Physical Cable Connection

Signal Name

Pin #

I/O

Signal Description

TX+

Transmit Plus. Differential outputs for FX, 100BaseTx, or 10BaseT transmission.

TX–

Transmit Minus. Differential outputs for FX, 100BaseTx, or 10BaseT transmission.

RX+

Receive Plus. Differential inputs for FX, 100BaseTx, or 10BaseT reception.

RX–

Receive Minus. Differential inputs for FX, 100BaseTx, or 10BaseT reception.

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