PCD5013 datasheet(18/76 Pages) PHILIPS

18 / 76 page

1999 Apr 12

Philips Semiconductors

Product speciﬁcation

FLEX

™ roaming decoder II

PCD5013

8.4.4

CONFIGURATION PACKET (ID = 01H)

The configuration packet defines a number of different

configuration options for the PCD5013. The PCD5013

ignores this packet when decoding is enabled,

i.e. the ON bit in the control packet is set (Table 12).

DFC: disable fractional clock (Table 8). When this bit is set

and IDE is set, the CLKOUT signal generates a 40 kHz

signal (EXTAL divided-by-4). When this bit is cleared and

IDE is set, the CLKOUT signal generates a 38.4 kHz signal

(EXTAL fractionally divided by 25

⁄6). This bit has no effect

when IDE is cleared. Value after reset = 0.

IDE: internal demodulator enable (Table 8). When this bit

is set, the internal demodulator is enabled and the clock

frequency at EXTAL is expected to be 160 kHz. When this

bit is cleared, the internal demodulator is disabled and the

clock frequency at EXTAL is expected to be 76.8 kHz.

Value after reset = 0.

OFD: oscillator frequency difference (Tables 4 and 8).

These bits represent the maximum frequency difference

between the 76.8 kHz oscillator (accounting for ageing,

temperature variation, manufacturing tolerance etc.) and

the worst case transmitter bit rate (specified as

±25 parts

per million (ppm) in the FLEX

™ specification).

For example, if the transmitter tolerance is

±25 ppm and

the 76.8 kHz oscillator tolerance is

±140 ppm, the

transmitter-oscillator frequency difference is

±165 ppm

and OFD should be cleared (300 ppm maximum). Value

after reset = 0. Note that configuring a smaller frequency

difference in this packet results in lower power

consumption due to higher receiver battery save ratios.

Table 4

Oscillator frequency difference

PCE: partial correlation enable (Table 8). When this bit is

set, partial correlation of addresses is enabled. When

partial correlation is enabled, the PCD5013 shuts down

the receiver before the end of the last FLEX

™ block which

contains addresses if it can determine that none of the

addresses in that FLEX

™ block matches any enabled

address in the PCD5013. When this bit is cleared, the

receiver is controlled as in the PCD5008. Value after

reset = 0.

OFD1

OFD0

FREQUENCY DIFFERENCE

(ppm)

±300

±150

±75

±0

SP: signal polarity (Tables 8, 5 and 6). These bits set the

polarity of EXTS1 and EXTS0 input signals. The polarity of

the EXTS1 and EXTS0 bits is determined by the receiver

design. Value after reset = 0.

Table 5

Input signal polarity

Table 6

FLEX

™ 4 level FSK modulation (SP = 00)

SME: synchronous mode enable (Table 8). When this bit

is set, a status packet is sent automatically whenever the

synchronous mode update (SMU) bit in the status packet

is set. This happens whenever a change occurs in the

synchronous mode (SM) status bit, which indicates that

the decoder is synchronized to a FLEX

™ data stream.

The host can use the SM bit in the status packet as an

in-range/out-of-range indication. Value after reset = 0.

COD: clock output disable (Table 8). When this bit is

cleared, a 38.4 or 40 kHz signal is output on the

CLKOUT pin (depending on the values of IDE and DFC).

When this bit is set, the CLKOUT pin is driven LOW. Value

after reset = 0.

• Setting and clearing this bit can cause pulses on the

CLKOUT pin that are less than one half the 38.4 kHz

period.

• When the clock output is enabled and not set for

intermittent operation (see ICO in this packet), the

CLKOUT pin always outputs the clock signal even when

the PCD5013 is in reset (as long as a clock signal is

available to the PCD5013 oscillator).

• When the PCD5013 is used in internal demodulator

mode (i.e. uses a 160 kHz oscillator), the CLKOUT pin

is 80 kHz from reset until the time the IDE bit is set.

SP1

SP0

SIGNAL POLARITY

EXTS1

EXTS0

normal

inverted

normal

inverted

EXTS1

EXTS0

DEVIATION

(Hz)

+4800

+1600

−1600

−4800

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