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PCD5013 датащи(PDF) 44 Page - NXP Semiconductors |
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PCD5013 датащи(HTML) 44 Page - NXP Semiconductors |
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44 / 76 page ![]() 1999 Apr 12 44 Philips Semiconductors Product specification FLEX ™ roaming decoder II PCD5013 8.7.7 SHORT INSTRUCTION VECTOR V: these bits are set 001 for a short instruction vector. WN: word number of vector (2 to 87 decimal) (Table 46). WN describes the location of the vector word in the frame. e: error (Table 46). Set if more than 2-bit errors are detected in the word, if the check character calculation fails after error correction has been performed, or if the vector value is determined to be invalid. p: phase (Table 46). This is the phase on which the vector was found (0 = A, 1 = B,2=Cand3=D). i: instruction type (Tables 46 and 47). These bits define the meaning of the d bits in this packet. x: unused bits (Table 46). The value of these bits is not guaranteed. d: data bits whose definition depend on the value of the i bits in this packet according to Table 47. Note that if this vector is received on a long address and the e bit in this packet is not set, the decoder sends a message packet immediately following the vector packet. All message bits in the message packet are unused and should be ignored. Table 46 Short instruction vector packet bit assignments Table 47 Short instruction vector definitions Notes 1. Assigned temporary address index a and associated frame number f (Section 8.8.5). 2. Refer to ”FLEX ™ Protocol specification G1.9”. BYTE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 30 WN6 WN5 WN4 WN3 WN2 WN1 WN0 2e p1 p0 xx V2 V1 V0 1x x d10 d9 d8 d7 d6 d5 0d4 d3 d2 d1 d0 i2 i1 i0 i2 i1 i0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 DESCRIPTION 000 a3 a2 a1 a0 f6 f5 f4 f3 f2 f1 f0 temporary address assignment, note 1 001 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 system event; note 2 010 a3 a2 a1 a0 f6 N5 N4 N3 N2 N1 N0 temporary address with message sequence number; note 2 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved for test |
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