AT91 datasheet(12/153 Pages) ATMEL

12 / 153 page

AT91X40 Series

1354D–ATARM–08/02

Peripheral Interrupt Control

The Interrupt Control of each peripheral is controlled from the status register using the

interrupt mask. The status register bits are ANDed to their corresponding interrupt mask

bits and the result is then ORed to generate the Interrupt Source signal to the Advanced

Interrupt Controller.

The interrupt mask is read in the Interrupt Mask Register and is modified with the Inter-

rupt Enable Register and the Interrupt Disable Register. The enable/disable/status (or

mask) makes it possible to enable or disable peripheral interrupt sources with a non-

interruptible single instruction. This eliminates the need for interrupt masking at the AIC

or Core level in real-time and multi-tasking systems.

Peripheral Data Controller

The AT91X40 Series Microcontroller has a 4-channel PDC dedicated to the two on-chip

USARTs. One PDC channel is dedicated to the receiver and one to the transmitter of

each USART.

The user interface of a PDC channel is integrated in the memory space of each USART.

It contains a 32-bit Address Pointer Register (RPR or TPR) and a 16-bit Transfer

Counter Register (RCR or TCR). When the programmed number of transfers are per-

formed, a status bit indicating the end of transfer is set in the USART Status Register

and an interrupt can be generated.

System Peripherals

PS: Power-saving

The Power-saving feature optimizes power consumption, enabling the software to stop

the ARM7TDMI clock (Idle Mode) and restarting it when the module receives an inter-

rupt (or reset). It also enables on-chip peripheral clocks to be enabled and disabled

individually, matching power consumption and application needs.

AIC: Advanced Interrupt

Controller

The AIC has an 8-level priority, individually maskable, vectored interrupt controller, and

drives the NIRQ and NFIQ pins of the ARM7TDMI from:

•

The external fast interrupt line (FIQ)

•

The three external interrupt request lines (IRQ0 - IRQ2)

•

The interrupt signals from the on-chip peripherals

The AIC is extensively programmable, offering maximum flexibility, and its vectoring fea-

tures reduce the real-time overhead in handling interrupts.

The AIC also features a spurious vector, which reduces spurious interrupt handling to a

minimum, and a protect mode that facilitates the debug capabilities.

PIO: Parallel IO Controller

The AT91X40 Series has 32 programmable I/O lines. Six pins are dedicated as general-

purpose I/O pins. Other I/O lines are multiplexed with an external signal of a peripheral

to optimize the use of available package pins. The PIO controller enables generation of

an interrupt on input change and insertion of a simple input glitch filter on any of the PIO

pins.

WD: Watchdog

The Watchdog is built around a 16-bit counter, and is used to prevent system lock-up if

the software becomes trapped in a deadlock. It can generate an internal reset or inter-

rupt, or assert an active level on the dedicated pin NWDOVF. All programming registers

are password-protected to prevent unintentional programming.

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