AT91 datasheet(77/153 Pages) ATMEL

77 / 153 page

AT91X40 Series

1354D–ATARM–08/02

Note:

Bit Number refers to the data bit that corresponds to this signal in each of the User Interface registers.

Table 10. Multiplexed Parallel I/Os

PIO Controller

Peripheral

Reset State

Number

Bit

Number

(1)

Port Name

Signal Description

Signal Direction

TCLK0

Timer 0 Clock signal

Input

PIO Input

TIOA0

Timer 0 Signal A

Bi-directional

PIO Input

TIOB0

Timer 0 Signal B

Bi-directional

PIO Input

TCLK1

Timer 1 Clock signal

Input

PIO Input

TIOA1

Timer 1 Signal A

Bi-directional

PIO Input

TIOB1

Timer 1 Signal B

Bi-directional

PIO Input

TCLK2

Timer 2 Clock signal

Input

PIO Input

TIOA2

Timer 2 Signal A

Bi-directional

PIO Input

TIOB2

Timer 2 Signal B

Bi-directional

PIO Input

IRQ0

External Interrupt 0

Input

PIO Input

P10

IRQ1

External Interrupt 1

Input

PIO Input

P11

IRQ2

External Interrupt 2

Input

PIO Input

P12

FIQ

Fast Interrupt

Input

PIO Input

P13

SCK0

USART 0 clock signal

Bi-directional

PIO Input

P14

TXD0

USART 0 transmit data signal

Output

PIO Input

P15

RXD0

USART 0 receive data signal

Input

PIO Input

P16

–

PIO Input

P17

–

PIO Input

P18

–

PIO Input

P19

–

PIO Input

P20

SCK1

USART 1 clock signal

Bi-directional

PIO Input

P21

TXD1

USART 1 transmit data signal

Output

PIO Input

P22

RXD1

USART 1 receive data signal

Input

PIO Input

P23

–

PIO Input

P24

–

PIO Input

P25

MCKO

Master Clock Output

Output

MCKO

P26

NCS2

Chip Select 2

Output

NCS2

P27

NCS3

Chip Select 3

Output

NCS3

100

P28

A20/CS7

Address 20/Chip Select 7

Output

A20

P29

A21/CS6

Address 21/Chip Select 6

Output

A21

P30

A22/CS5

Address 22/Chip Select 5

Output

A22

P31

A23/CS4

Address 23/Chip Select 4

Output

A23

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