PCA5010H datasheet(99/112 Pages) PHILIPS

99 / 112 page

1998 Nov 02

Philips Semiconductors

Product speciﬁcation

Pager baseband controller

PCA5010

Fig.68 Parallel programming mode.

handbook, full pagewidth

MGR351

PROGRAMMER

LS0

ADDL/ADDH/DATA I/O

LS1

PCA5010

P2.0

P0.0 to P0.7

P2.1

PGM

P2.2

RdStrb

P2.3

GBMbpB

P2.4

WEB

P2.5

SIG

P2.6

SEC

P2.7

MIN

PSEN

MOUT2

ALE

MOUT1

RESETN

RESETIN

CLOCK

TCLK, XTL1

VDD

VDD, VDDA, VDD(DC), VBAT

VSS

VSS, VSSA, VSS(DC)

VPP

15.3

Entering the parallel programming mode

The parallel programming mode has been implemented as

a general test mode of the PCA5010. This mode can be

entered by applying 000 to pins PSEN, ALE, and EA

during reset. For the initializing sequence a clock of

76.8 kHz at XTL1 is expected and the supply voltage VDD

must be higher then 2.2 V. At the rising edge of RESOUT

these signals are latched and the code 000 leads to

parallel programming mode. The high voltage pin VPP can

be either HIGH or VDD.

Since PSEN and ALE are output signals of the PCA5010

after reset, a pull-down (strong enough to overdrive the

internal 100

µA pull-up of the PCA5010) should be used to

drive the outputs LOW. Alternatively the LOW can be

driven with a 3-state buffer which is enabled with

RESOUT = LOW.

The microcontroller fetches instructions from Port 0 in

external mode. Data fetching is controlled by PSEN and

ALE. This is the standard data fetch in external mode.

A clock has to be supplied to TCLK while entering the

parallel programming mode. Before entering the parallel

programming mode, Port 2 should be set to 30H and the

microcontroller should be put in Idle mode by setting the bit

PCON.0 (address 87H).

The test mode is activated by making EA equal to logic 1.

The mode entering sequence is given in Table 65.

Before entering the parallel program mode Port 2 can be

an output port (dependent on the reset configuration of this

port). As soon as the parallel programmed mode is entered

Port 2 is an input.

After entering the parallel programming mode this mode

has to be initialized. The OTP test latch has to be loaded

with code 01H to set the sense amplifiers in verify mode.

Before a byte can be programmed a verify has to be

performed to check if programming is not blocked by the

security (see Section 15.10). The address of this verify

cycle is not important and the address latches do not have

to be loaded. After this initialization the PCA5010 is ready

for programming. Parallel program initialization is shown in

Fig.71.

The security check can be replaced by another read action

e.g reading the security or signature bytes (see

Section 15.9).

It should be noted that this paragraph is only

applicable for the first series. It can be neglected in the

future. To prevent problems with the self timed loop it is

advised to set the circuit in DC read mode during verify.

This is achieved by writing 09H instead of 01H into the

OTP test latch.

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