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PCA5010H датащи(PDF) 59 Page - NXP Semiconductors |
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PCA5010H датащи(HTML) 59 Page - NXP Semiconductors |
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59 / 112 page ![]() 1998 Nov 02 59 Philips Semiconductors Product specification Pager baseband controller PCA5010 6.20 Idle and power-down operation Idle and power-down are power saving modes of the microcontroller that can be activated when no CPU activity is required. Both modes do not stop the 76.8 kHz oscillator nor disable any peripheral function. The following functions remain active during the Idle mode: • Timer 0 and Timer 1 • Wake-up counter • Watchdog counter • Real-time clock • Demodulator and clock recovery • UART • I2C-bus • External interrupt. 6.20.1 IDLE MODE The instruction that sets PCON.0 is the last instruction executed in the normal operating mode before the Idle mode is activated. Once in the Idle mode, the CPU status is preserved together with the stack pointer, program counter, program status word and accumulator. The RAM and all other registers maintain their data during Idle mode. The status of the external pins during Idle mode is shown in Table 51. There are two ways to terminate the Idle mode: 1. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware thus terminating the Idle mode. The interrupt is serviced, and following the RETI instruction, the next instruction to be executed will be the one following the instruction that put the device in the Idle mode. The flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When the Idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. 2. The second way of terminating the Idle mode is with an internal or external hardware reset. Reset redefines all SFRs but does not affect the on-chip RAM. Possible sources of an internal reset are a) Watchdog reset if the watchdog had expired b) Off/on reset if the DC/DC converter is restarted from off mode (wake-up counter, RTC or P1 pins). 6.20.2 POWER-DOWN MODE The instruction that sets PCON.1 is the last instruction executed in the normal operating mode before the power-down mode is activated. Once in the power-down mode, the CPU status is preserved together with the stack pointer, program counter, program status word and accumulator. The RAM and all other registers maintain their data during power-down mode. The status of the external pins during power-down mode is shown in Table 51. There are two ways to terminate the power-down mode: 1. Activation of an enabled external interrupt [INT2 to INT9] will cause PCON.1 to be cleared by hardware thus terminating the power-down mode. The interrupt is serviced, and following the RETI instruction, the next instruction to be executed will be the one following the instruction that put the device in the power-down mode. 2. The second way of terminating the power-down mode is with an internal or external hardware reset. Reset redefines all SFRs but does not affect the on-chip RAM. Possible sources of an internal reset are a) Watchdog reset if the watchdog had expired b) Off/on reset if the DC/DC converter is restarted from off mode (wake-up counter or P1 pins). The power-down mode is not specially useful. It has been implemented for compatibility only. The Idle mode has the same power saving capability and allows much more flexible wake-up. 6.20.3 OFF MODE The off mode has been designed as the power saving mode of the PCA5010. Shortly after entering this mode the DC/DC converter is switched off and VDD is reduced to VBAT. Directly after activating the off mode, the CPU must be set in Idle mode. The off mode is entered by: 1. ORL DCCON0, #80H 2. ORL PCON, #01H. The off mode can be exited by one of the following events: • RTC minute event • Wake-up counter event • Event on any P1 pin • RESETIN active HIGH. |
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