CIRCC datasheet(33/70 Pages) SMSC

33 / 70 page

No Wait, bit 3

When the No Wait bit is one, the ISA Bus

nSRDY signal goes active following the trailing

edge of the ISA I/O command and inactive

following the rising edge (see the Zero Wait State

Support section on page 65).

String Move, Bit 2

When

the

String

Move

bit

one,

the

programmed I/O host interface is qualified by

IOCHRDY (Table 21). See the IOCHRDY Time-

Out section on page 63.

DMA Burst Mode, bit 1

When the DMA Burst Mode bit is one, DMA

Burst (Demand) mode is enabled.

When the

DMA Burst Mode bit is zero, Single Byte DMA

mode is enabled (Table 21). See the DMA

section on page 58.

DMA Enable, bit 0

DMA Enable is connected to a signal in the

Interface Description called DMAEN that is used

by the chip-level interface to tristate the CIrCC

DMA

controls

when

the

DMA

interface

inactive. When the DMA Enable bit is one, the

DMA host interface is active (Table 21). See the

DMA section on page 58.

When the DMA

Enable bit is zero (default), the nDACK and TC

inputs are disabled and DRQ output is gated off.

Table 21 - I/O Interface Modes

STRING

MOVE

DMA

BURST

DMA

ENABLE

FUNCTION

Programmed I/O, no IOCHRDY

Programmed I/O, uses IOCHRDY

Single Byte DMA Mode

Demand Mode DMA

FIFO Threshold Register (Address 2)

The

FIFO

Threshold

contains

the

programmable FIFO threshold count. The FIFO

threshold is programmable from 0 to 31. Bits 6

and 7 in the FIFO Threshold register are read-

only and will always return zero. FIFO Threshold

values

typically

reflect

the

overall

I/O

performance characteristics of the host; the lower

the value, the longer the interval between service

requests and the faster the host must be to

successfully service them. The same threshold

value can be used for both I/O read and I/O write

cases.

FIFO COUNT Register (Address 3)

The

FIFO

COUNT

represents

the

remaining number of data bytes in the 128-byte

SCE FIFO. When the FIFO COUNT is 0x00 the

FIFO is empty. When the FIFO is full the FIFO

COUNT

0x80.

The

FIFO

COUNT

independent of the data flow direction.

For

example, if the FIFO COUNT is 0x0A during

transmit there are ten bytes to send; if the FIFO

COUNT is 0x0A during receive there are ten

bytes to read.

Tx PW Limit, bit 6

The Tx PW Limit bit enables hardware designed

to restrict the IR transmit pulse width (see the

Transmit Pulse Width Limit section on page 67).

If Tx PW Limit = 0, The TRANSMIT PULSE

WIDTH LIMIT hardware is defeated and no

transmit pulse width restrictions are made. If Tx

PW Limit = 1, The TRANSMIT PULSE WIDTH

LIMIT hardware will prevent pulses larger than

100Fs with a 25% duty cycle from appearing at

the IRCC TX output ports.

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