CIRCC datasheet(29/70 Pages) SMSC

29 / 70 page

Message Count, bits 0 - 3

The four Message Count bits control (internal)

hardware access to the Line Status Registers

and are unaffected by the Status Register

Address. The Message Count bits also indicate

the system message-state. For example, if the

Message Count bits are zero, i.e. the power-up

default, Line Status Register zero is active,

although undefined because no messages have

been sent or received. The Message Count bits

are incremented after every active frame.

point A in Figure 18, for example, the rising edge

of nActive Frame increments Message Count by

one indicating that the first message has been

received. This means that Line Status Register

#1 (status register address 0) is valid, and Line

Status Register #2 is currently active, although

undefined.

Hardware prevents the Message

Count

from

exceeding

eight

('1000'Binary).

Bus Status Register (Address 6)

FIFO Indicators (read-only)

The FIFO Indicators reflect the current status of

the SCE FIFO.

FIFO Not Empty, bit 7

The FIFO Not Empty bit when set to one

indicates that there is data in the SCE FIFO.

FIFO Full, bit 6

The FIFO Full bit when set to one indicates that

there is no room for data in the SCE FIFO.

Time-Out, bit 5

The Time-Out bit is the IOCHRDY time-out error

bit. The Time-Out bit when set to one indicates

that an IOCHRDY time-out error has occurred

(see the IOCHRDY Time-Out section on page

63).

Time-Out is reset by the CIrCC System

Reset, following a read of the Bus Status

nActive Frame

Message Count (0000)

0001

0010 0011

FIGURE 18 - MESSAGE COUNT EXAMPLE

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