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AM29PDL640G датащи(PDF) 47 Page - Advanced Micro Devices |
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AM29PDL640G датащи(HTML) 47 Page - Advanced Micro Devices |
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47 / 61 page ![]() December 13, 2005 Am29PDL640G 45 D A TA SH EE T AC CHARACTERISTICS Hardware Reset (RESET#) Note: Not 100% tested. Parameter Description All Speed Options Unit JEDEC Std t Ready RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns t RP RESET# Pulse Width Min 500 ns t RH Reset High Time Before Read (See Note) Min 50 ns t RPD RESET# Low to Standby Mode Min 20 µs t RB RY/BY# Recovery Time Min 0 ns RESET# RY/BY# RY/BY# tRP tReady Reset Timings NOT during Embedded Algorithms tReady CE#, OE# tRH CE#, OE# Reset Timings during Embedded Algorithms RESET# tRP tRB Figure 14. Reset Timings |
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