L800BT90VC datasheet(13/49 Pages) AMD

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Am29LV800B

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command reg-

ister itself does not occupy any addressable memory

location. The register is composed of latches that

store the commands, along with the address and data

information needed to execute the command. The

contents of the register serve as inputs to the internal

state machine. The state machine outputs dictate the

function of the device. Table 1 lists the device bus

operations, the inputs and control levels they require,

and the resulting output. The following subsections

describe each of these operations in further detail.

Table 1. Am29LV800B Device Bus Operations

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1. Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configu-

ration. If the BYTE# pin is set at logic ‘1’, the device

is in word configuration, DQ15–DQ0 are active and

controlled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device. OE# is the output

control and gates array data to the output pins. WE#

should remain at VIH. The BYTE# pin determines

whether the device outputs array data in words or

bytes.

The internal state machine is set for reading array

data upon device power-up, or after a hardware

reset. This ensures that no spurious alteration of the

memory content occurs during the power transition.

No command is necessary in this mode to obtain

array data. Standard microprocessor read cycles that

assert valid addresses on the device address inputs

produce valid data on the device data outputs. The

device remains enabled for read access until the

command register contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to Figure 13 for the timing diagram. ICC1 in

the DC Characteristics table represents the active

current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more

information.

Operation

CE# OE#

RESET#

Addresses

(Note 1)

DQ0–

DQ7

DQ8–DQ15

BYTE#

= VIH

BYTE#

= VIL

Read

AIN

DOUT

DQ8–DQ14 = High-Z,

DQ15 = A-1

Write

AIN

DIN

Standby

VCC ±

0.3 V

VCC ±

0.3 V

High-Z

Output Disable

High-Z

Reset

High-Z

Sector Protect (Note 2)

VID

Sector Address,

A6 = L, A1 = H,

A0 = L

DIN

Sector Unprotect (Note 2)

VID

Sector Address,

A6 = H, A1 = H,

A0 = L

DIN

Temporary Sector Unprotect

VID

AIN

DIN

High-Z

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