L800BT90VC datasheet(21/49 Pages) AMD

21 / 49 page

Am29LV800B

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip

erase command, which in turn invokes the Embedded

Erase algorithm. The device does not require the

system to preprogram prior to erase. The Embedded

Erase algorithm automatically preprograms and veri-

fies the entire memory for an all zero data pattern

prior to electrical erase. The system is not required to

provide any controls or timings during these opera-

tions. Table 1 shows the address and data require-

ments for the chip erase command sequence.

Any commands written to the chip during the

Embedded Erase algorithm are ignored. Note that a

hardware reset during the chip erase operation

immediately terminates the operation. The Chip

Erase command sequence should be reinitiated once

the device has returned to reading array data, to

ensure data integrity.

The system can determine the status of the erase

operation by using DQ7, DQ6, DQ2, or RY/BY#. See

“Write Operation Status” for information on these

status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data

and addresses are no longer latched.

Figure 4 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and to Figure 18 for

timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. Table 1 shows the address and data

requirements for the sector erase command

sequence.

The device does not require the system to prepro-

gram the memory prior to erase. The Embedded

Erase algorithm automatically programs and verifies

the sector for an all zero data pattern prior to elec-

trical erase. The system is not required to provide any

controls or timings during these operations.

After the command sequence is written, a sector

erase time-out of 50 µs begins. During the time-out

period, additional sector addresses and sector erase

commands may be written. Loading the sector erase

buffer may be done in any sequence, and the number

of sectors may be from one sector to all sectors. The

time between these additional cycles must be less

than 50 µs, otherwise the last address and command

might not be accepted, and erasure may begin. It is

recommended that processor interrupts be disabled

during this time to ensure all commands are

accepted. The interrupts can be re-enabled after the

last Sector Erase command is written. If the time

between additional sector erase commands can be

assumed to be less than 50 µs, the system need not

monitor DQ3. Any command other than Sector

Erase or Erase Suspend during the time-out

period resets the device to reading array data.

The system must rewrite the command sequence and

any additional sector addresses and commands.

The system can monitor DQ3 to determine if the

sector erase timer has timed out. (See the “DQ3:

Sector Erase Timer” section.) The time-out begins

from the rising edge of the final WE# pulse in the

command sequence.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. Note that a hardware reset

during the sector erase operation immediately termi-

nates the operation. The Sector Erase command

sequence should be reinitiated once the device has

returned to reading array data, to ensure data integ-

rity.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses

are no longer latched. The system can determine the

status of the erase operation by using DQ7, DQ6,

DQ2, or RY/BY#. Refer to “Write Operation Status”

for information on these status bits.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section for parameters, and

to Figure 18 for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to

interrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during

the Sector Erase time-out immediately terminates

the time-out period and suspends the erase opera-

tion. Addresses are “don’t-cares” when writing the

Erase Suspend command.

When the Erase Suspend command is written during

a sector erase operation, the device requires a

maximum of 20 µs to suspend the erase operation.

However, when the Erase Suspend command is

written during the sector erase time-out, the device

immediately terminates the time-out period and sus-

pends the erase operation.

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device

“erase suspends” all sectors selected for erasure.)

Normal read and write timings and command defini-

tions apply. Reading at any address within erase-sus-

pended sectors produces status data on DQ7–DQ0.

The system can use DQ7, or DQ6 and DQ2 together,

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