USB97C201 datasheet(47/59 Pages) SMSC

47 / 59 page

SMSC USB97C201

Page 47

Rev. 11-05-03

DATASHEET

STROBE: This is a data strobe signal driven by the TRANSMITTER of a data transfer, which is either the IDE device

of a DMA Read transfer or the USB97C201 of a DMA Write transfer, on which data is transferred during each rising

and falling edge transition of the signal. The IORDY signal is redefined as STROBE for reads (when transferring data

from the IDE device to the USB97C201). The IDE_nIOR signal is redefined as STROBE for writes (transferring data

from the USB97C201 to the IDE device).

nDMARDY: This is a signal driven by the RECEIVER of a data transfer, which is either the USB97C201 of a DMA

Read transfer or the IDE device of a DMA Write transfer, to signal that the RECEIVER is ready to transfer data or to

add wait states to the current transaction. The IDE_nIOR signal is redefined as nDMARDY for reads (when

transferring data from the IDE device to the USB97C201). The IORDY signal is redefined as nDMARDY for writes

(transferring data from the USB97C201 to the IDE device).

Table 63 – ULTRA ATA/66 Control Signal Assignments

STANDARD

IDE SIGNAL

NAME

SIGNAL NAME

DURING ULTRA

ATA/66 READ

CYCLE

SIGNAL NAME

DURING ULTRA

ATA/66 WRITE

CYCLE

IDE_nIOW

STOP

IDE_nIOR

nDMARDY

STROBE

IORDY

STROBE

nDMARDY

Note:

“Ultra ATA/66 Read Cycle”: Data transfers are from the IDE device to the USB97C201.

“Ultra ATA/66 Write Cycle”: Data transfers are from the USB97C201 to the IDE device.

6.3.6

ULTRA ATA/66 OPERATION

After initialization, there are two primary operations provided by the Ultra ATA/66 controller: data transfers and cyclic

redundancy checking (CRC).

6.3.6.1

Initialization

Initialization includes enabling and performing proper set up on the USB97C201and the IDE device. For the

USB97C201, it is necessary to enable Ultra ATA/66 mode for the IDE device and setting up the Ultra ATA/66 cycle

timings through the ATA_DMA register. The USB97C201 supports five timing modes: Mode 0 (120ns cycle time),

Mode 1 (80 ns cycle time), Mode 2 (60ns cycle time), Mode 3 (45ns cycle time), and Mode 4 (30ns cycle time).

6.3.6.2

Data Transfer Operation

The USB97C201 and the Ultra ATA compatible IDE device control the transfer via the Ultra ATA protocol. The actual

data transfer consists of three phases, a start-up phase, a data transfer phase, and a burst termination phase.

Start-Up Phase: The IDE device begins the start-up phase by asserting DRQ signal. When ready to begin the

transfer, the USB97C201 will assert nDACK. When nDACK is asserted, the USB97C201 will drive CS0/1

inactive, and A0-A2 low.

For Write cycles, the USB97C201 will deassert STOP, wait for the IDE device to assert nDMARDY and then

drive the first data word and the STROBE signal.

For Read cycles, the USB97C201will tristate the data lines, deassert STOP, and assert nDMARDY. The IDE

device will then drive the first data word and the STROBE signal.

Data-Transfer Phase: The burst data transfer continues with the data source (Writes: USB97C201, Reads: IDE

devices) providing data and toggling STROBE. Data is transferred (latched by receiver) on each rising and falling

edge of STROBE.

The source can pause the burst stream by holding STROBE high or low, resuming the burst stream by again

toggling STROBE.

The receiver can pause the burst stream by negating the nDMARDY and resumes the transfers by asserting

nDMARDY.

The USB97C201 may pause a burst transaction in order to toggle internal data buffer, or to prevent a buffer over or

under flow condition, resuming once the condition has cleared.

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