USB97C201 datasheet(46/59 Pages) SMSC

46 / 59 page

SMSC USB97C201

Page 46

Rev. 11-05-03

DATASHEET

Table 62 – IDE Transaction Timing

IDE TRANSACTION TYPE

STARTUP

LATENCY

ISP

RCT

SHUTDOWN

LATENCY

Non-Data Port Compatible

133ns

367ns

733ns

67ns

Data Port Compatible

100ns

200ns

467ns

67ns

Fast Timing Mode (for Data Port

Accessing)

67ns

267-167ns

33-133ns

67ns

6.3.3

PIO IDE DATA PREFETCHING AND POSTING

The IDE Controller can be programmed via the IDE_TIM registers to allow data to be posted to and prefetched from

the IDE data ports. Data prefetching is initiated when a data port read occurs. The read prefetch eliminates latency to

the IDE data ports and allows them to be performed back to back for the highest possible PIO data transfer rates. The

first data port read of a sector is called the demand read. Subsequent data port reads from the sector are called

prefetch reads. The demand read and all prefetch reads must be of the same size (16 or 32 bits).

Data posting is performed for writes to the IDE data ports. The IDE CONTROLLER will then run the IDE cycle to

transfer the data to the drive.

6.3.4

DMA TRANSFERS

When enabled and supported by the device, DMA transfers are executed on the IDE interface, the chip selects

(IDE_nCS1/0) will be negated (high). When the IDE device asserts IDE_DRQ, the IDE Controller will return

IDE_nDACK to the IDE device when it is ready for the DMA data transfer. For multiword DMA transfers, the

IDE_nIOR or IDE_nIOW signal will free run at the programmed rate as long as IDE_DRQ remains asserted and the

IDE Controller is prepared to complete a data transfer. If IDE_DRQ has not de-asserted by the rising edge of

IDE_nIOR or IDE_nIOW signal multiword DMA is assumed and at least one more cycle will be executed. If IDE_DRQ

de-asserts before IDE_nIOR or IDE_nIOW is de-asserted while IDE_nDACK is asserted, it indicates that one last

data transfer remains for the current session. In this case, IDE_nDACK will be de-asserted one clock after the

IDE_nIOR or IDE_nIOW signal de-asserts. This allows the IDE controller to support both single and multiword DMA

cycles automatically.

The IDE device’s DMA request signal is sampled when the IO strobe is deasserted. If inactive, the DMA Acknowledge

signal is deasserted and no more transfers take place until DMA request is again asserted.

The controller transfers data to or from the EP2 buffer(s) responding to the DMA requests from the IDE device. The

controller will continue this until stopped or the byte count in ATA_CNT[3:0] reaches zero.

6.3.4.1

Completion of DMA Data Transfers

The IDE device signals an interrupt (IDE_IRQ) once its programmed data count has been transferred or an error

occurs. The IDE device will also deassert its DMA request signal, causing the IDE Controller to stop transferring data.

On reads from the IDE device, it will cause any data read from the device to be transferred to the EP2 buffer(s), as

they become available.

6.3.5

ULTRA ATA/66 SYNCHRONOUS DMA OPERATION

Ultra ATA/66 is a new IDE transfer protocol used to transfer data between a Ultra ATA/66 capable IDE controller and

Ultra ATA/66 capable IDE devices. Ultra DMA/66 utilizes a “source synchronous” signaling protocol to transfer data at

rates up to 66 Mbytes/sec.

6.3.5.1

Ultra ATA/66 Signals

Although no additional signal pins are required for Ultra ATA/66 operation, the operation of some standard IDE

controller pins are redefined during Ultra ATA modes of operation. The Ultra DMA/66 protocol defines three hand-

shaking signals: STOP, STROBE and DMARDY. Table 63 shows the mapping of the redefined Ultra ATA/66 signals

onto the standard IDE controller pins.

STOP: STOP is always driven by the the USB97C201 and is used to request that a transfer be stopped or as an

acknowledgment to stop a request from IDE device. The IDE_nIOW signal is redefined as STOP for both read and

write transfers.

USB97C201 датащи(PDF) 46 Page - SMSC Corporation

USB97C201 датащи(HTML) 46 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

датащи скачать

ссылки URL