20

3053B–MICRO–3/05

AT89LS51

Note:

1. B1 = 0, B2 = 0

B1 = 0, B2 = 1

B1 = 1, B2 = 0

B1 = 1, B1 = 1

After Reset signal is high, SCK should be low for at least 64 system clocks before it goes high to clock in the enable data

bytes. No pulsing of Reset signal is necessary. SCK should be no faster than 1/16 of the system clock at XTAL1.

For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper address byte are

latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. Then the next instruction will be ready

to be decoded.

Table 19-1.

Serial Programming Instruction Set

Instruction

Instruction Format

Operation

Byte 1

Byte 2

Byte 3

Byte 4

Programming Enable

1010 1100

0101 0011

xxxx xxxx

xxxx xxxx

0110 1001

(Output on MISO)

Enable Serial Programming

while RST is high

Chip Erase

1010 1100

100x xxxx

xxxx xxxx

xxxx xxxx

Chip Erase Flash memory

array

Read Program Memory

(Byte Mode)

0010 0000

xxxx

Read data from Program

memory in the byte mode

Write Program Memory

(Byte Mode)

0100 0000

xxxx

Write data to Program

memory in the byte mode

Write Lock Bits

(1)

1010 1100

1110 00

xxxx xxxx

xxxx xxxx

Write Lock bits (see Note 1)

Read Lock Bits

0010 0100

xxxx

xxxx

xxxx xxxx

xxx

xx

Read back current status of

the lock bits (a programmed

lock bit reads back as a “1”)

Read Signature Bytes

0010 1000

xxxx

xxx xxx0

Signature Byte

Read Signature Byte

Read Program Memory

(Page Mode)

0011 0000

xxxx

Byte 0

Byte 1...

Byte 255

Read data from Program

memory in the Page Mode

(256 bytes)

Write Program Memory

(Page Mode)

0101 0000

xxxx

Byte 0

Byte 1...

Byte 255

Write data to Program

memory in the Page Mode

(256 bytes)

before Mode 4 can be executed.