13

3053B–MICRO–3/05

AT89LS51

Figure 11-2. External Clock Drive Configuration

12. Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The

mode is invoked by software. The content of the on-chip RAM and all the special function regis-

ters remain unchanged during this mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-

gram execution from where it left off, up to two machine cycles before the internal reset

algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but

access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a

port pin when idle mode is terminated by a reset, the instruction following the one that invokes

idle mode should not write to a port pin or to external memory.

13. Power-down Mode

In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down

is the last instruction executed. The on-chip RAM and Special Function Registers retain their

values until the Power-down mode is terminated. Exit from Power-down mode can be initiated

either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset

redefines the SFRs but does not change the on-chip RAM. The reset should not be activated

before V

the oscillator to restart and stabilize.

XTAL2

XTAL1

GND

NC

EXTERNAL

OSCILLATOR

SIGNAL

Table 13-1.

Status of External Pins During Idle and Power-down Modes

Mode

Program Memory

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

Idle

Internal

1

1

Data

Data

Data

Data

Idle

External

1

1

Float

Data

Address

Data

Power-down

Internal

0

0

Data

Data

Data

Data

Power-down

External

0

0

Float

Data

Data

Data