9

3053B–MICRO–3/05

AT89LS51

6.

Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K

bytes each of external Program and Data Memory can be addressed.

6.1

Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory.

On the AT89LS51, if EA is connected to V

FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are

directed to external memory.

6.2

Data Memory

The AT89LS51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct

and indirect addressing modes. Stack operations are examples of indirect addressing, so the

128 bytes of data RAM are available as stack space.

7.

Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to

software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset

(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user

must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When

the WDT is enabled, it will increment every machine cycle while the oscillator is running. The

WDT timeout period is dependent on the external clock frequency. There is no way to disable

the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-

flows, it will drive an output RESET HIGH pulse at the RST pin.

Table 5-3.

AUXR1: Auxiliary Register 1

AUXR1

Address = A2H

Reset Value = XXXXXXX0B

Not Bit

Addressable

––

––

–

–

–

DPS

Bit

7

6

5

4

3

2

1

0

–

Reserved for future expansion

DPS

Data Pointer Register Select

DPS

0

Selects DPTR Registers DP0L, DP0H

1

Selects DPTR Registers DP1L, DP1H