Not

4-50

Program Memory Lock Bits

On the chip are three lock bits which can be left unpro-

grammed (U) or can be programmed (P) to obtain the addi-

tional features listed in the table below:

Note:

1.

The lock bits can only be erased with the Chip Erase

operation.

When lock bit 1 is programmed, the logic level at the EA pin

is sampled and latched during reset. If the device is pow-

ered up without a reset, the latch initializes to a random

value, and holds that value until reset is activated. It is nec-

essary that the latched value of EA be in agreement with

the current logic level at that pin in order for the device to

function properly.

Programming the Flash

The AT89LV51 is normally shipped with the on-chip Flash

memory array in the erased state (i.e. contents=FFH) and

ready to be programmed.

The respective top-side marking and device signature

codes are listed below:

The AT89LV51 code memory array is programmed byte-

by-byte. To program any non-blank byte in the on-chip

Flash Code Memory, the entire memory must be erased

using the Chip Erase Mode.

Programming Algorithm: Before programming the

AT89LV51, the address, data and control signals should be

set up according to the Flash programming mode table and

Figure 3 and Figure 4. To program the AT89LV51, the fol-

lowing sequence should be followed:

1.

Input the desired memory location on the address

lines.

2.

Input the appropriate data byte on the data lines.

3.

Activate the correct combination of control signals.

4.

5.

Pulse ALE/PROG once to program a byte in the Flash

array or the lock bits. The byte-write cycle is self-timed

and typically takes no more than 1.5 ms. Repeat steps

1 through 5 changing the address and data for the

entire array or until the end of the object file is reached.

Data Polling: The AT89LV51 features Data Polling to indi-

cate the end of a write cycle. During a write cycle, an

attempted read of the last byte written will result in the com-

plement of the written data on PO.7. Once the write cycle

has been completed, true data is valid on all outputs, and

the next cycle may begin. Data Polling may begin any time

after a write cycle has been initiated.

Ready/Busy: The progress of byte programming can also

be monitored by the RDY/BSY output signal. P3.4 is pulled

low after ALE goes high during programming to indicate

BUSY. P3.4 is pulled high again when programming is

done to indicate READY.

Program Verify: If lock bits LB1 and LB2 have not been

programmed, the programmed code data can be read back

via the address and data lines for verification. The lock bits

cannot be verified directly. Verification of the lock bits is

achieved by observing that their features are enabled.

Chip Erase:

The entire Flash array and the lock bits are

erased electrically by using the proper combination of con-

trol signals and by holding ALE/PROG low for 10 ms. The

code array is written with all “1”s. The chip erase operation

must be executed before the code memory can be re-pro-

grammed.

Reading the Signature Bytes: The signature bytes are

read by the same procedure as a normal verification of

locations 030H and 031H, except that P3.6 and P3.7 need

to be pulled to a logic low. The values returned are:

(030H) = 1EH indicates manufactured by Atmel

(031H) = 61H indicates 89LV51

(032H) = FFH indicates 12V programming

Program Lock Bits

Protection Type

LB1

LB2

LB3

1

U

U

U

No program lock features.

2

P

U

U

MOVC instructions executed

from external program

memory are disabled from

fetching code bytes from

internal memory, EA is

sampled and latched on

reset, and further

programming of the Flash is

disabled.

3

P

P

U

Same as mode 2, also verify

is disabled.

4

P

P

P

Same as mode 3, also

external execution is

disabled.

Top-Side Mark

AT89LV51

xxxx

yyww

Signature

(030H) = 1EH

(031H) = 61H

(032H) = FFH