Not

4-48

External Access Enable. EA must be strapped to GND in

order to enable the device to fetch code from external pro-

gram memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is programmed, EA will be

internally latched on reset.

tions.

This pin also receives the 12-volt programming enable volt-

gramming is selected.

XTAL1

Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Special Function Registers

A map of the on-chip memory area called the Special Func-

tion Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc-

cupied addresses may not be implemented on the chip.

Read accesses to these addresses will in general return

random data, and write accesses will have an indetermi-

nate effect.

User software should not write 1s to these unlisted loca-

tions, since they may be used in future products to invoke

new features. In that case, the reset or inactive values of

the new bits will always be 0.

Timer 0 and 1

Timer 0 and Timer 1 in the AT89LV51 operate the same

way as Timer 0 and Timer 1 in the AT89C51.

Table 1. AT89LV51 SFR Map and Reset Values

0F8H

0FFH

0F0H

B

00000000

0F7H

0E8H

0EFH

0E0H

ACC

00000000

0E7H

0D8H

0DFH

0D0H

PSW

00000000

0D7H

0C8H

T2CON

00000000

T2MOD

XXXXXX00

RCAP2L

00000000

RCAP2H

00000000

TL2

00000000

TH2

00000000

0CFH

0C0H

0C7H

0B8H

IP

XX000000

0BFH

0B0H

P3

11111111

0B7H

0A8H

IE

0X000000

0AFH

0A0H

P2

11111111

0A7H

98H

SCON

00000000

SBUF

XXXXXXXX

9FH

90H

P1

11111111

97H

88H

TCON

00000000

TMOD

00000000

TL0

00000000

TL1

00000000

TH0

00000000

TH1

00000000

8FH

80H

P0

11111111

SP

00000111

DPL

00000000

DPH

00000000

PCON

0XXX0000

87H