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The AT89LV51 provides the following standard features:

4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-

bit timer/counters, a five vector two-level interrupt architec-

ture, a full duplex serial port, on-chip oscillator and clock

circuitry. In addition, the AT89LV51 is designed with static

logic for operation down to zero frequency and supports

two software selectable power saving modes. The Idle

Mo de st ops th e CPU wh ile allo win g th e RAM,

timer/counters, serial port and interrupt system to continue

functioning. The Power Down Mode saves the RAM con-

tents but freezes the oscillator disabling all other chip func-

tions until the next hardware reset.

Pin Description

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an

output port each pin can sink eight TTL inputs. When 1s

are written to port 0 pins, the pins can be used as high-

impedance inputs.

Port 0 may also be configured to be the multiplexed low-

order address/data bus during accesses to external pro-

gram and data memory. In this mode P0 has internal pul-

lups.

Port 0 also receives the code bytes during Flash program-

ming, and outputs the code bytes during program verifica-

tion. External pullups are required during program verifica-

tion.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups.

The Port 1 output buffers can sink/source four TTL inputs.

When 1s are written to Port 1 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 1 pins that are externally being pulled low will source

Port 1 also receives the low-order address bytes during

Flash programming and verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups.

The Port 2 output buffers can sink/source four TTL inputs.

When 1s are written to Port 2 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 2 pins that are externally being pulled low will source

Port 2 emits the high-order address byte during fetches

from external program memory and during accesses to

external data memory that use 16-bit addresses (MOVX @

DPTR). In this application it uses strong internal pullups

when emitting 1s. During accesses to external data mem-

ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the

contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some

control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups.

The Port 3 output buffers can sink/source four TTL inputs.

When 1s are written to Port 3 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 3 pins that are externally being pulled low will source

Port 3 also serves the functions of various special features

of the AT89LV51 as listed below:

Port 3 also receives some control signals for Flash pro-

gramming and verification.

RST

Reset input. A high on this pin for two machine cycles while

the oscillator is running resets the device.

ALE/PROG

Address Latch Enable output pulse for latching the low byte

of the address during accesses to external memory. This

pin is also the program pulse input (PROG) during Flash

programming.

In normal operation ALE is emitted at a constant rate of 1/6

the oscillator frequency, and may be used for external tim-

ing or clocking purposes. Note, however, that one ALE

pulse is skipped during each access to external Data Mem-

ory.

PSEN

Program Store Enable is the read strobe to external pro-

gram memory.

When the AT89LV51 is executing code from external pro-

gram memory, PSEN is activated twice each machine

cycle, except that two PSEN activations are skipped during

each access to external data memory.

Port Pin

Alternate Functions

P3.0

RXD (serial input port)

P3.1

TXD (serial output port)

P3.2

INT0 (external interrupt 0)

P3.3

INT1 (external interrupt 1)

P3.4

T0 (timer 0 external input)

P3.5

T1 (timer 1 external input)

P3.6

WR (external data memory write strobe)

P3.7

RD (external data memory read strobe)