WM8581 datasheet(52/100 Pages) WOLFSON

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WM8581

Production Data

PD Rev 4.0 April 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

06h

7:4

PLL_N[3:0]

0111

Integer (N) part of PLLB frequency

ratio (R).

Use values in the range 5 ≤ PLLB_N

≤ 13 as close as possible to 8

Note: PLLB_N must be set to

specific values when the S/PDIF

receiver is used. Refer to S/PDIF

Receive Mode Clocking section

for details.

Table 41 User Mode PLL_K and PLL_N Multiplier Control

Parameter

PLL User Mode

PLL S/PDIF Receiver Mode

PRESCALE_A

Manual

Write PRESCALE_B Value

PRESCALE_B

Manual

Configure Specified PLLB Frequency

PLLA_N

Manual

Automatically Controlled

PLLA_K

Manual

Automatically Controlled

PLLB_N

Manual

Configure Specified PLLB Frequency

PLLB_K

Manual

Configure Specified PLLB Frequency

FREQMODE_A

Manual

Automatically Controlled

FREQMODE_B

Manual

Not Used

POSTSCALE_A

Manual

256fs/128fs PLLACLK Select

POSTSCALE_B

Manual

Not Used

Table 42 PLL Control Register Function in PLL User and PLL S/PDIF Receiver Modes

PLL CONFIGURATION

The PLLs perform a configurable frequency multiplication of the input clock signal (f1). The

multiplication factor of the PLL (denoted by ‘R’) is variable and is defined by the relationship: R = (f2 ÷

f1).

The multiplication factor for each PLL is set using register bits PLLx_N and PLLx_K (refer to Table 41). The

multiplication effect of both the N and K multipliers are additive (i.e. if N is configured to provide a

multiplication factor of 8 and K is configured to provide a multiplication factor of 0.192, the overall

multiplication factor is 8 + 0.192 = 8.192).

In order to choose and configure the correct values for PLLx_N and PLLx_K, multiplication factor R

must first be calculated. Once value R is calculated, the value of PLLx_N is the integer (whole

number) value of R, ignoring all digits to the right of the decimal point. For example, if R is calculated

to be 8.196523, PLL_N is simply 8.

Once PLLx_N is calculated, the PLLx_K value is simply the integer value of (222 (R-PLLx_N)). For

example, if R is 8.196523 and PLLx_N is 8, PLLx_K is therefore (2

22 (8.196523-8)), which is 824277

(ignoring all digits to the right of the decimal point).

Note:

the PLLs are designed to operate with best performance (shortest lock time and optimum

stability) when f2 is between 90 and 100MHz and PLLx_N is 8. However, acceptable PLLx_N values

lie in the range 5 ≤ PLLx_N ≤ 13.

Each PLL has an output divider to allow the f2 clock signal to be divided to a frequency suitable for

use as the source for the MCLK and CLKOUT outputs, the S/PDIF transmitter and the internal ADC

and DACs. The divider output is configurable and is set by the FREQMODE_A or FREQMODE_B

bits in conjunction with the POSTSCALE_A and POSTSCALE_B bits. Each PLL is also equipped

with a pre-scale divider which offers frequency divide by one or two before the OSCCLK signal is

input into the PLL. Please refer to Table 43 for details.

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