WM8581 datasheet(44/100 Pages) WOLFSON

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WM8581

Production Data

PD Rev 4.0 April 2007

R15

RX2DAC_MODE

DAC Rate and Power down control

(only valid when DAC_SRC = 00)

0 = SFRM_CLK determines rate,

DACs 2/3/4 powered down

1 = PAIFRX_LRCLK determines

rate, DACs 2/3/4 source PAIFRX

Table 33 DAC Clock Control

ADC INTERFACE

The ADC_CLKSEL register selects the ADC clock source from ADCMCLK, PLLACLK, PLLBCLK, or

ADCMCLK. However, if the S/PDIF receiver is powered up, the PLLACLK and PLLBCLK are invalid

for ADC operation, so the choice is limited to ADCMCLK (default) or MCLK. The rate that the ADC

operates at is determined by the ADC Rate module. It calculates the rate based on the digital routing

setup. If the ADC is sourced by the PAIF Transmitter, PAIFTX_LRCLK is used in the rate calculation.

If the ADC is sourced by the SAIF Transmitter (and PAIF Transmitter has another source),

SAIF_LRCLK is used in the rate calculation. If the S/PDIF Transmitter (only) is sourcing the ADC,

then the rate is set by the ADC_RATE register bits.

The ADC clock source can be independent from the DACs and PLLs, however for optimum

performance, it is recommended that where possible, clock sources on the WM8581 are

synchronous. Performance may be degraded if this condition is not met.

Figure 27 ADC Clock Selection

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3:2

ADC_CLKSEL

ADC clock source

00 = ADCMLCK pin

01 = PLLACLK

10 = PLLBCLK

11 = MCLK pin

R29

7:5

ADCRATE[2:0]

010

ADC Rate Control (only used when

the S/PDIF Tx is the only interface

sourcing the ADC)

000 = 128fs

001 = 192fs

010 = 256fs

011 = 384fs

100 = 512fs

101 = 768fs

110 = 1152fs

Table 34 ADC Clock Control

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