STM32G431C6 datasheet(43/198 Pages) STMICROELECTRONICS

43 / 198 page

DS12589 Rev 6

43/198

STM32G431x6 STM32G431x8 STM32G431xB

Functional overview

The digital controller handles notably:

•

USB Type-C level detection with de-bounce, generating interrupts

•

FRS detection, generating an interrupt

•

Byte-level interface for USB Power Delivery payload, generating interrupts (DMA

compatible)

•

USB Power Delivery timing dividers (including a clock pre-scaler)

•

CRC generation/checking

•

4b5b encode/decode

•

Ordered sets (with a programmable ordered set mask at receive)

•

Frequency recovery in receiver during preamble

The interface offers low-power operation compatible with Stop mode, maintaining the

capacity to detect incoming USB Power Delivery messages and FRS signaling.

3.36

Clock recovery system (CRS)

The devices embed a special block which allows automatic trimming of the internal 48 MHz

oscillator to guarantee its optimal accuracy over the whole device operational range. This

automatic trimming is based on the external synchronization signal, which could be either

derived from USB SOF signalization, from LSE oscillator, from an external signal on

CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also

possible to combine automatic trimming with manual trimming action.

3.37

Development support

3.37.1

Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could

be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with

SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to

switch between JTAG-DP and SW-DP.

3.37.2

Embedded trace macrocell™

The Arm embedded trace macrocell provides a greater visibility of the instruction and data

flow inside the CPU core by streaming compressed data at a very high rate from the

STM32G431x6/x8/xB devices through a small number of ETM pins to an external hardware

trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded

and then formatted for display on the host computer that runs the debugger software. TPA

hardware is commercially available from common development tool vendors.

The Embedded trace macrocell operates with third party debugger software tools.

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