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DS20005020C-page 7

SST39VF3201C/SST39VF3202C

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by-block)

basis. The SST39VF3201C/SST39VF3202C offer both Sector-Erase and Block-Erase mode. The sector architecture is

based on uniform sector size of 2 KWord. The Block-Erase mode is based on block sizes of 4 and 32 KWord. The Sec-

tor-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (50H) and sec-

tor address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence

with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched

on the falling edge of the sixth WE# pulse, while the command (50H or 30H) is latched on the rising edge of the sixth

WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be deter-

mined using either Data# Polling or Toggle Bit methods. See Figure 11 and Figure 12 for timing waveforms and

Figure 25 for the flowchart. Any commands issued during the Sector- or Block-Erase operation are ignored. When WP#

is low, any attempt to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP#

should be statically held high or low.

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read

from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The

operation is executed by issuing one byte command sequence with Erase-Suspend command (B0H). The device auto-

matically enters Read mode typically within 10 µs after the Erase-Suspend command had been issued. Valid data can

be read from any sector or block that is not suspended from an Erase operation. Reading at address location within

erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at ‘1’. While in Erase-Suspend mode, a Word-Pro-

gram operation is allowed except for the sector or block selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation that has been suspended, the system must issue a Erase Resume

command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at

any address in the last Byte sequence.

Chip-Erase Operation

The SST39VF3201C/SST39VF3202C provide a Chip-Erase operation, which allows the user to erase the entire mem-

ory array to the ‘1’ state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command (10H) at

address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#,

whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 7 for the

command sequence, Figure 10 for timing diagram and Figure 25 for the flowchart. Any commands issued during the

Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-Erase will be ignored. During the command

sequence, WP# should be statically held high or low.

Write Operation Status Detection

The SST39VF3201C/SST39VF3202C provide two software means to detect the completion of a Write (Program or Erase)

cycle, in order to optimize the system write cycle time. The software detection includes two Status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write Detection mode is enabled after the rising edge of WE#, which initiates

the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Tog-

gle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an

erroneous result (i.e., valid data may appear to conflict with either DQ7 or DQ6). In order to prevent spurious rejection,

if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two

(2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST39VF3201C/SST39VF3202C are in the internal Program operation, any attempt to read DQ7 will produce

the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even

though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs

may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs.

During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is com-