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DS20005020C-page 21

SST39VF3201C/SST39VF3202C

FIGURE 12:

WE# CONTROLLED SECTOR ERASE TIMING DIAGRAM

FIGURE 13:

SOFTWARE ID ENTRY AND READ

2: This device also supports CE# controlled Sector Erase operation The WE# and CE# signals are interchangeable as long

as minimum timings are met. (see Table 18)

SAX = Block Address

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

ADDRESSES

DQ15-0

WE#

555

2AA

2AA

555

555

XX55

XX50

XX55

XXAA

XX80

XXAA

SAX

OE#

CE#

RY/BY#

VALID

SIX-BYTE CODE FOR SECTOR-ERASE

TWP

TSE

TBY

TBR

Note 1: Device ID = 235E for SST39VF3201C and 235E for SST39VF3202C.

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

ADDRESS

TIDA

DQ15-0

WE#

SW0

SW1

SW2

555

2AA

555

0000

0001

OE#

CE#

Three-Byte Sequence for Software ID Entry

TWP

TWPH

TAA

00BF

Device ID

XX55

XXAA

XX90