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DS20005020C-page 2

SST39VF3201C/SST39VF3202C

DESCRIPTION

The SST39VF3201C and SST39VF3202C devices are 2M x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured

with proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling

injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF3201C/

SST39VF3202C write (Program or Erase) with a 2.7V-3.6V power supply. These devices conform to JEDEC standard

pin assignments for x16 memories.

Featuring high-performance Word Program, the SST39VF3201C/SST39VF3202C devices provide a typical Word Pro-

gram time of 7 µsec. These devices use Toggle Bit, Data# Polling or RY/BY# pin to indicate the completion of Program

operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes.

Designed, manufactured and tested for a wide spectrum of applications, these devices are offered with a typical endur-

ance of 100,000 cycles. Data retention is rated at greater than 100 years.

The SST39VF3201C/SST39VF3202C devices are suited for applications that require convenient and economical updat-

ing of program, configuration or data memory. For all system applications, they significantly improve performance and

reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alterna-

tive Flash technologies. The total energy consumed is a function of the applied voltage, current and time of application.

Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase

time, the total energy consumed during any Erase or Program operation is less than alternative Flash technologies.

These devices also improve flexibility while lowering the cost for program, data and configuration storage applications.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program

cycles that have occurred. Therefore, the system software or hardware does not have to be modified or derated as is

necessary with alternative Flash technologies, whose Erase and Program times increase with accumulated Erase/Pro-

gram cycles.

To meet high-density, surface mount requirements, the SST39VF3201C/SST39VF3202C devices are offered in 48-lead

TSOP and 48-ball TFBGA packages. See Figure 2 and Figure 3 for pin assignments.

BLOCK DIAGRAM

FIGURE 1:

FUNCTIONAL BLOCK DIAGRAM

Y-Decoder

I/O Buffers and Data Latches

Address Buffer & Latches

X-Decoder

DQ15 - DQ0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

WP#

RESET#

RY/BY#

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